如何编写一个makefile文件,C文件都在src和.h文件在INC文件夹? [英] How to write a single makefile, c files are in src and h files are in inc folder?
问题描述
我试图写一个makefile应该从挑选的src /和头源来自INC /
〜/ Linuz / src目录:1.C,2.C,3.C ...
〜/ Linuz / INC:abc.h,dyz.h
请帮我创造这应该是可以在
一个makefile〜/ Linuz / some_other_dir / Makefile文件
PS:试图编译它为我的Linux机器
。感谢您的建议。
所有:my_program%的.o:../src/%.c
$(CC)$(CFLAGS)-I ../ INC / -c -o $ @ $ ^my_program:1.O 3.O 2.O
$(CC)$(LDFLAGS)-o $ @ $ ^清洁:
RM -f *的.o my_program
如果你把你的Makefile在〜/ Linuz / some_other_dir / ,以下规则
%○:。../src/%.c
会从 ../的src /
文件夹中的C文件(〜/ Linuz / src目录/ ),并创建对象(* .o)文件在Makefile中的同一文件夹中。
的 -I ../ INC /
选项意味着生成文件CANL从 ../ INC / $得到一个头文件C $ C>文件夹(〜/ Linuz / INC / )。
的 my_program:1.O 3.O 2.O
规则意味着生成文件将创建的Makefile从对象文件相同的目录二进制 1.O
和 2.O
和 3.O
从<一个href=\"http://www.gnu.org/software/make/manual/html_node/Automatic-Variables.html#Automatic-Variables\"相对=nofollow>进行手动:
$ ^ 所有的prerequisites的名称,它们之间的空间。
对于prerequisites这是归档成员,只有指定的成员是
(请参阅档案)。将目标对对方只有一个prerequisite
文件这取决于,不管每个文件被多少次列为
prerequisite。所以,如果你列出一个prerequisite不止一次了
目标的$ ^值只包含一个名称的副本。这个列表
不包含任何的顺序仅prerequisites的;对于那些看
在`$ |'变量,下文。
$ @ 的规则的目标的文件名。如果目标是一个
归档成员,那么$ @是归档文件的名称。在一个
有多个目标模式规则(见简介模式
规则),$ @是取其目标的名字引起了规则的食谱
要运行
块引用>I am trying to write a makefile which should pick the sources from src/ and headers from inc/
~/Linuz/src: 1.c, 2.c, 3.c ...
~/Linuz/inc: abc.h, dyz.h
Please help me to create a makefile which should be available at
~/Linuz/some_other_dir/Makefile
PS: Trying to compile it for my linux machine.
Thank you for your suggestions.
解决方案all: my_program %.o: ../src/%.c $(CC) $(CFLAGS) -I../inc/ -c -o $@ $^ my_program: 1.o 2.o 3.o $(CC) $(LDFLAGS) -o $@ $^ clean: rm -f *.o my_program
If you put your Makefile in the ~/Linuz/some_other_dir/, the following rule
%.o: ../src/%.c
will get the c files from the
../src/
folder (~/Linuz/src/) and create the object (*.o) files in the same folder of the Makefile.The
-I../inc/
option means that the makefile canl get a header files from the../inc/
folder (~/Linuz/inc/).The
my_program: 1.o 2.o 3.o
rule means that the makefile will create the binary in the same directory of Makefile from the object files1.o
and2.o
and3.o
From the make manual:
$^ The names of all the prerequisites, with spaces between them. For prerequisites which are archive members, only the member named is used (see Archives). A target has only one prerequisite on each other file it depends on, no matter how many times each file is listed as a prerequisite. So if you list a prerequisite more than once for a target, the value of $^ contains just one copy of the name. This list does not contain any of the order-only prerequisites; for those see the `$|' variable, below.
$@ The file name of the target of the rule. If the target is an archive member, then ‘$@’ is the name of the archive file. In a pattern rule that has multiple targets (see Introduction to Pattern Rules), ‘$@’ is the name of whichever target caused the rule's recipe to be run.
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