GCC不能向量化64位乘法。可以64位x 64位 - > 128位扩展乘法在AVX2上向量化？ [英] GCC couldn't vectorize 64-bit multiplication. Can 64-bit x 64-bit -> 128-bit widening multiplication be vectorized on AVX2?

问题描述

我尝试向量化一个使用64位扩展乘法的CBR​​NG。

  static __inline__ uint64_t mulhilo64（uint64_t a，uint64_t b， uint64_t * hip）{
 __uint128_t product =（（__uint128_t）a）*（（__ uint128_t）b）; 
 * hip = product>> 64; 
 return（uint64_t）product;这样的乘法是以AVX2中的向量化形式存在的吗？
 
解决方案
否。没有64 x 64  - > 128位算法作为向量指令。也不是有一个向量 mulhi 类型指令（高字的乘法结果）。
 
 
 
 [V] PMULUDQ可以做32 x 32  - > 64位，只考虑每隔32位无符号元素或无符号双字作为源，并将每个64位结果扩展为两个结果元素，组合为无符号四字。
 
 
 
现在最好的是Haswell的MULX指令，它具有更灵活的寄存器使用，不会影响标志寄存器 - 消除一些停顿。
 
I try to vectorize a CBRNG which uses 64bit widening multiplication.
static __inline__ uint64_t mulhilo64(uint64_t a, uint64_t b, uint64_t* hip) {
    __uint128_t product = ((__uint128_t)a)*((__uint128_t)b);
    *hip = product>>64;
    return (uint64_t)product;
}
Is such a multiplication exists in a vectorized form in AVX2?
解决方案
No. There's no 64 x 64 -> 128 bit arithmetic as a vector instruction. Nor is there a vector mulhi type instruction (high word result of multiply).

[V]PMULUDQ can do 32 x 32 -> 64 bit by only considering every second 32 bit unsigned element, or unsigned doubleword, as a source, and expanding each 64 bit result into two result elements combined as an unsigned quadword.

The best you can probably hope for right now is Haswell's MULX instruction, which has more flexible register use, and does not affect the flags register - eliminating some stalls.

                        
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