调试VHDL：怎么样？ [英] Debugging VHDL: How to?

问题描述

我是VHDL的新手，不知道如何调试VHDL代码。

有没有任何软件可能会让我深入了解内部我的VHDL实体的信号随着时间的流逝或类似的东西？

请帮助。

解决方案

正如其他帖子指出的那样，您可能需要模拟器如 GHDL 。但是，为了调试您的模拟，有一些不同的方法：

• 经典打印语句 - - 在程序代码中混合 writeline（output，[...]）。 看到这个你好世界的例子如果你只是开始，然后添加打印语句将是无价的。对于大多数我所做的模拟调试（这是我的工作的一部分），我几乎完成了基于我们在设计中构建的打印语句的调试，以及 testbench 。它只适用于最终的调试，或者是使用下一个调试方法的更困难的问题。




• 转储模拟（为GHDL看到这个页面和这个）。这是您的设计（或您的设计的一个子集）的循环跟踪。就像您将逻辑分析仪连接到设计中的每一条线路 em>。所有的信息，你可能想要你的设计，但在一个非常低的水平 - 信号水平。要使用这种方法：

  
  

  1. 创建一个模拟转储。这种转储的基本格式是更改转储或VCD 。无论您使用哪种模拟器，您都需要阅读有关如何创建VCD的文档。 （您也可以在文档中搜索转储 - 您的模拟器可能会使用不同的文件格式进行转储。）

  
  

  2. 创建模拟转储后然后，您将转储加载到波形查看器中。如果您使用 gEDA软件包，那么您将使用 gtkwave 查看转储。

  
  







note 如果要使用GHDL和gtkwave调试VHDL代码，可以将它们安装在 ubuntu 命令：

 ％sudo apt-get install geda ghdl 
  

（假设你有root访问运行ubuntu的机器）




I am a newbie to VHDL and can't figure out how to debug VHDL code.

Is there any software that could probably give me an insight to the internal signals of my VHDL entity as time passes or something like that?

Please help.

解决方案

As the other posts have pointed out, you'll likely need a simulator like GHDL. However, to debug your simulation, there are a few different methodologies:

• Classic print statements -- just mix in writeline(output,[...]) in your procedural code. See this hello world example. If you're just getting started, then adding print statements will be invaluable. For most of the simulation debug that I do ( and that is part of my job ), I do almost all of the debug based on print statements that we've built up in our design and testbench. It is only for the final debug, or for more difficult issues that I use the next debug method.

• "Dumping" the simulation ( for GHDL see this page and this one ). This is a cycle by cycle trace of your design ( or a subset of your design). It's as if you hook up a logic analyzer to every single wire in your design. All the info you could ever want about your design, but at a very low level -- the signal level. To use this methodology:

  1. Create a simulation "dump". The base format for such a dump is a Value Change Dump or VCD. Whichever simulator you use, you'll need to read the documentation on how to create a VCD. ( You can also search "dump" in your docs -- your simulator may use a different file format for its dumps.)

  2. Once you create a simulation dump, you then load your dump into a wave-form viewer. If you're using the gEDA package, then you would use gtkwave to view the dump.

note If you want to use GHDL and gtkwave to debug your VHDL code, you can install them on ubuntu with command:

% sudo apt-get install geda ghdl

( assuming you have root access to the machine running ubuntu)

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