在VHDL中的< =和= =之间有什么区别？ [英] What' s the difference between <= and := in VHDL

问题描述

目前，我正在使用VHDL学习一些FPGA设计技术，我的问题是我们是否可以在VHDL中使用：=和< =可互换，尽管我已经看到在常量声明中使用：=， =在作业中？感谢提前！

解决方案

规则比这更复杂一点，但基本上：你使用 < = 进行信号分配，其在下一个增量循环中生效。您使用：= 进行变量赋值，这将立即进行。所以如果你有一个信号，你总是使用< = 。如果你有一个变量，你总是使用：= 。

有些地方不太符合您通常会遇到一些初始化问题，其中：= 甚至用于信号。

所以：

  signal some_signal：std_logic：='0'; -  0初始值
 ... 
变量some​​_variable：std_logic：='0'; -  0初始值
 ... 
 some_signal< ='1'; - 将在下一个时间段（delta循环）中分配1 
 ... 
 some_variable：='1'; - 立即分配1 
  

Currently, I am learning some FPGA design techniques using VHDL, my problem is whether we can use := and <= interchangeably in VHDL or not, though I've seen the use of := in constants declarations and <= in assignments? Thanks in advance!

解决方案

The rules are a little more complex than this, but basically: you use <= to do signal assignment, which takes effect on the next delta cycle. You use := to do variable assignment, which takes place immediately. So if you have a signal, you always use <=. If you have a variable, you always use :=.

Some places where this is not quite that case that you will commonly run into, for instance, initialization, where := is used even for signals.

So:

signal some_signal : std_logic := '0'; -- 0 initial value
...
variable some_variable : std_logic := '0'; -- 0 initial value
...
some_signal <= '1'; -- will assign 1 at the next time step (delta cycle)
...
some_variable := '1'; -- assigns 1 immediately

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