一般JTAG在嵌入式开发系统中的工作流程？ [英] General JTAG working flow in an embedded development system?

问题描述

在我的嵌入式项目中，我使用JTAG界面下载代码并调试下载的应用程序。但是我不知道在JTAG设置中发生了什么。

<任何人都可以给我JTAG设置的基本想法/流程（高级视图），这将真正帮助我更好地了解我的开发系统。

__ Kanu

解决方案

要添加到Cliffords的答案，这里有一些照片：

http://www.fpga4fun.com/JTAG2.html

Tap控制器状态机是您将看到发布的恶心的东西。这是JTAG的关键。正如Clifford所说你访问片上调试寄存器。抽头控制器状态机与所有JTAG支持的器件通用，但是可以通过JTAG获取寄存器的地址，长度等。为了做某些有用的事情，您必须阅读或写入的事情的顺序从供应商到供应商都有很大差异。一些ARM技术参考手册（用于各种内核）例如具有调试TAP控制器章节，具有该图片以及用于读取和写入寄存器或存储器或暂停处理器等的程序的详细信息。

In my embedded project am using JTAG interface to download the code and to debug the downloaded application.But i don't know what is happening inside the JTAG set up.

Can anyone please give me basic idea/flow(high level view) of the JTAG set up wich will really help me to understand my development system better.

__Kanu

解决方案

To add to Cliffords answer, there are some pictures here:

http://www.fpga4fun.com/JTAG2.html

The tap controller state machine is something you will see published ad nauseum. It is really the key to JTAG. As Clifford said you access on chip debug registers. The tap controller state machine is generic to all JTAG supported devices, but the address, length, etc of the registers you can get to through JTAG. And the sequence of things you have to read or write in order to do something useful varies widely from vendor to vendor. Some ARM Technical Reference Manuals (for various cores) for example have a Debug TAP controller chapter, with this picture and with the gory details on the procedure for reading and writing a register or memory or halting the processor, etc.

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