CPU和数据比对 [英] CPU and Data alignment
问题描述
请原谅我，如果你觉得这已经回答了无数次，但我需要回答以下查询！
Pardon me if you feel this has been answered numerous times, but I need answers to the following queries!
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为什么数据对齐（4字节/ 8字节/ 2字节边界）？在这里，我的疑问是当CPU地址线斧-1 AX-2 ... A2 A1 A0则是完全可能的顺序寻址存储器位置。那么，为什么有需要在特定的边界对齐数据？
Why data has to be aligned (on 4 byte/ 8 byte/ 2 byte boundaries)? Here my doubt is when the CPU has address lines Ax Ax-1 Ax-2 ... A2 A1 A0 then it is quite possible to address the memory locations sequentially. So why there is the need to align the data at specific boundaries?
如何找到对齐要求时，我编我的code和产生executatble？
How to find the alignment requirements when I am compiling my code and generating the executatble?
如果对于如数据对齐为4字节边界，这是否意味着每个连续字节位于模4偏移？我的疑问是，如果数据是4字节对齐的意思是，如果一个字节是1004则下一个字节是1008（或1005）？
If for e.g the data alignment is 4 byte boundary, does that mean each consecutive byte is located at modulo 4 offsets? My doubt is if data is 4 byte aligned does that mean that if a byte is at 1004 then the next byte is at 1008 (or at 1005)?
您的想法是远迎。
在此先感谢！ / MS
Thanks in advance! /MS
推荐答案
CPU都面向字的，而不是面向字节的。在一个简单的CPU，存储器通常被配置为返回一个字的（32位，64位等）每地址选通信，其中，底部的两个（或更多个）地址线一般不 - 护理比特。
CPUs are word oriented, not byte oriented. In a simple CPU, memory is generally configured to return one word (32bits, 64bits, etc) per address strobe, where the bottom two (or more) address lines are generally don't-care bits.
英特尔的CPU可以对非单词边界值的许多指令访问，但是有一个性能损失为内部的CPU执行两个存储器存取和数学运算来加载一个字。如果你正在做字节读取，没有对齐适用。
Intel CPUs can perform accesses on non-word boundries for many instructions, however there is a performance penalty as internally the CPU performs two memory accesses and a math operation to load one word. If you are doing byte reads, no alignment applies.
某些CPU（ARM，还是Intel的SSE指令）要求对齐的存储空间，并已做未对齐的访问时，未定义操作（或抛出异常）。他们节省显著硅空间不执行要复杂得多加载/存储子系统。
Some CPUs (ARM, or Intel SSE instructions) require aligned memory and have undefined operation when doing unaligned accesses (or throw an exception). They save significant silicon space by not implementing the much more complicated load/store subsystem.
对齐取决于CPU字长（16，32，64位），或在上海证券交易所的情况下，SSE寄存器的大小（128位）。
Alignment depends on the CPU word size (16, 32, 64bit) or in the case of SSE the SSE register size (128 bits).
有关你的最后一个问题，如果你是在一次加载一个数据字节没有对大多数CPU没有对齐限制（部分的DSP没有字节级指令，但它有可能你不会遇到一个）。
For your last question, if you are loading a single data byte at a time there is no alignment restriction on most CPUs (some DSPs don't have byte level instructions, but its likely you won't run into one).
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