用变量在VHDL中使用FOR循环 [英] Using FOR loop in VHDL with a variable

问题描述

  for i in 0 to some_var loop $ b是否有任何可能的方法来创建一个for循环$ b // blah，blah 
 end loop; 
  

如果不是，还有其他方法可以创建相同的循环吗？由于While循环允许使用变量作为限制，但它们在我的项目中不能合成。

在此先感谢，

Bojan Matovski

解决方案

综合你可以通过使用静态范围和退出条件获得相同的效果。将范围设置为您将需要的最大值。

  for i in 0 to MAX_VALUE loop 
 exit i = some_var; 
 // blah，blah 
 end loop; 
  

如果您的综合工具扼杀了这个，请提交一个错误报告。 1076.6-1999和1076.6-2004（VHDL RTL综合标准）都指出出口条件支持具有静态范围的for循环。您可能会发现有关使用循环标签（1076.6-1999）的支持问题表示不支持。

如果您发现错误（或缺乏支持）并且不报告，您的供应商会认为这是您不关心的功能，不会投资改变他们的工具。

Is there any possible way to create a for loop in the form:

for i in 0 to some_var loop
    // blah,blah
end loop;

If not, is there any alternative way to create the same loop? Since While loops allows to use variable as the limit, but they are not synthesizeable in my project.

Thanks in Advance,

Bojan Matovski

解决方案

The variable works just fine for testbench applications.

For synthesis you can get the same effect by using a static range and an exit condition. Set the range to be the maximum you will need.

for i in 0 to MAX_VALUE loop
  exit when i = some_var ;
  // blah,blah
end loop;

If your synthesis tool chokes on this, file a bug report. Both 1076.6-1999 and 1076.6-2004 (VHDL RTL Synthesis Standards) indicate that exit conditions are supported for "for" loops with a static range. You may find support issues with respect to using a loop label (1076.6-1999) indicates it is not supported.

If you find a bug (or lack of support) and do not report it, your vendor will think it is a feature you don't care about, and hence, will not invest in changing their tool.

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