英特尔x86 0x2E / 0x3E前缀分支预测实际使用? [英] Intel x86 0x2E/0x3E Prefix Branch Prediction actually used?

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问题描述

在最新的英特尔软件开发手册中,它描述了两个操作码前缀:

 组2>分支提示

0x2E:分支未采取
0x3E:分支采取



<这些操作允许跳转指令的显式分支预测(操作码像 Jxx

我记得读了几个几年前,x86显式分支预测在gccs分支预测内在函数的上下文中基本上是不可操作的。



我不清楚这些x86分支提示是否是新的功能或者它们在实践中是否实际上没有任何操作。



任何人都可以清除它?



是:gccs分支预测函数是否生成这些x86分支提示? - 目前的英特尔CPU不会忽略它们吗? - 这是什么时候发生的?)

更新:

我创建了一个快速测试程序:

  int main(int argc,char ** argv)
{
if(__builtin_expect(argc,0))
return 1;

if(__builtin_expect(argc == 2,1))
return 2;

返回3;
}

反汇编如下:

  00000000004004cc< main> ;: 
4004cc:55 push%rbp
4004cd:48 89 e5 mov%rsp,%rbp
4004d0: 89 7d fc mov%edi,-0x4(%rbp)
4004d3:48 89 75 f0 mov%rsi,-0x10(%rbp)
4004d7:8b 45 fc mov -0x4(%rbp), %eax
4004da:48 98 cltq
4004dc:48 85 c0 test%rax,%rax
4004df:74 07 je 4004e8< main + 0x1c>
4004e1:b8 01 00 00 00 mov $ 0x1,%eax
4004e6:eb 1b jmp 400503< main + 0x37>
4004e8:83 7d fc 02 cmpl $ 0x2,-0x4(%rbp)
4004ec:0f 94 c0 sete%al
4004ef:0f b6 c0 movzbl%al,%eax
4004f2:48 85 c0 test%rax,%rax
4004f5:74 07 je 4004fe< main + 0x32>
4004f7:b8 02 00 00 00 mov $ 0x2,%eax
4004fc:eb 05 jmp 400503< main + 0x37>
4004fe:b8 03 00 00 00 mov $ 0x3,%eax
400503:5d pop%rbp
400504:c3 retq
400505:66 2e 0f 1f 84 00 00 nopw% cs:0x0(%rax,%rax,1)
40050c:00 00 00
40050f:90 nop

我没有看到2E或3E?也许gcc因为某种原因而忽略了它们?

解决方案

这些指令前缀对现代处理器(比Pentium 4更新) 。他们仅花费一个字节的代码空间,因此,不生成它们是正确的。



详细信息请参阅Agner Fog的优化手册,特别是3.微体系结构: http://www.agner.org/optimize/



英特尔®64和IA-32架构优化参考手册在有关优化分支的章节中不再提及它们(第3.4.1节):
http://www.intel.de/content/dam/doc/manual / 64-ia-32-architectures-optimization-manual.pdf



这些前缀是Netburst架构的一个(无害的)残余物。在全面优化中,您可以使用它们来对齐代码,但这就是现在所擅长的。


In the latest Intel software dev manual it describes two opcode prefixes:

Group 2 > Branch Hints

    0x2E: Branch Not Taken
    0x3E: Branch Taken

These allow for explicit branch prediction of Jump instructions (opcodes likeJxx)

I remember reading a couple of years ago that on x86 explicit branch prediction was essentially a no-op in the context of gccs branch prediciton intrinsics.

I am now unclear if these x86 branch hints are a new feature or whether they are essentially no-ops in practice.

Can anyone clear this up?

(That is: Does gccs branch prediction functions generate these x86 branch hints? - and do current Intel CPUs not ignore them? - and when did this happen?)

Update:

I created a quick test program:

int main(int argc, char** argv)
{
    if (__builtin_expect(argc,0))
        return 1;

    if (__builtin_expect(argc == 2, 1))
        return 2;

    return 3;
}

Disassembles to the following:

00000000004004cc <main>:
  4004cc:   55                      push   %rbp
  4004cd:   48 89 e5                mov    %rsp,%rbp
  4004d0:   89 7d fc                mov    %edi,-0x4(%rbp)
  4004d3:   48 89 75 f0             mov    %rsi,-0x10(%rbp)
  4004d7:   8b 45 fc                mov    -0x4(%rbp),%eax
  4004da:   48 98                   cltq   
  4004dc:   48 85 c0                test   %rax,%rax
  4004df:   74 07                   je     4004e8 <main+0x1c>
  4004e1:   b8 01 00 00 00          mov    $0x1,%eax
  4004e6:   eb 1b                   jmp    400503 <main+0x37>
  4004e8:   83 7d fc 02             cmpl   $0x2,-0x4(%rbp)
  4004ec:   0f 94 c0                sete   %al
  4004ef:   0f b6 c0                movzbl %al,%eax
  4004f2:   48 85 c0                test   %rax,%rax
  4004f5:   74 07                   je     4004fe <main+0x32>
  4004f7:   b8 02 00 00 00          mov    $0x2,%eax
  4004fc:   eb 05                   jmp    400503 <main+0x37>
  4004fe:   b8 03 00 00 00          mov    $0x3,%eax
  400503:   5d                      pop    %rbp
  400504:   c3                      retq   
  400505:   66 2e 0f 1f 84 00 00    nopw   %cs:0x0(%rax,%rax,1)
  40050c:   00 00 00 
  40050f:   90                      nop

I don't see 2E or 3E ? Maybe gcc has elided them for some reason?

解决方案

These instruction prefixes have no effect on modern processors (anything newer than Pentium 4). They just cost one byte of code space, and thus, not generating them is the right thing.

For details, see Agner Fog's optimization manuals, in particular 3. Microarchitecture: http://www.agner.org/optimize/

The "Intel® 64 and IA-32 Architectures Optimization Reference Manual" no longer mentions them in the section about optimizing branches (section 3.4.1): http://www.intel.de/content/dam/doc/manual/64-ia-32-architectures-optimization-manual.pdf

These prefixes are a (harmless) relict of the Netburst architecture. In all-out optimization, you can use them to align code, but that's all they're good for nowadays.

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