library ieee;
use ieee.std_logic_1164.all;

entity MUX is
	port(
		A: in std_logic;
		B: in std_logic;
		S: in std_logic;
		Z: out std_logic
	);
end MUX;

architecture main of MUX is
begin
	with S select Z <= A when '0', B when '1';
end main;