在Makefile中强制依赖项顺序 [英] Force order of dependencies in a Makefile

问题描述

我有一个Makefile，我想并行使用它来编译一组单独的程序.看起来像这样:

I have a Makefile that i want to use in parallel to compile a set of separate programs. It looks something like this:

compileall: program1 program2 program3
    @echo "Compilation completed"

program1 program2 program3:
    @echo "Compiling $@"
    $(MAKE) -C $@

我使用gmake compileall -j3调用它，一切正常.它每天都在我们的测试脚本中运行.

I call it using gmake compileall -j3 and everything works fine. It runs daily as a part of our testing script.

现在，我添加了一个新的目标program1a，它必须是同一make目标的一部分，并且不能与program1目标同时执行.它是在并行发生之前还是之后发生，这并不重要.

Now, I've added a new target program1a that needs to be a part of this same make target and must not be performed at the same time as the program1 target. It is not important if it happens before or after, just not in parallel.

我知道我可以做类似的事情:

I know I could do something like:

compileall:
    +$(MAKE) program1 program2 program3
    +$(MAKE) program1a
    @echo "Compilation completed"

program1 program2 program3:
    @echo "Compiling $@"
    $(MAKE) -C $@

program1a:
    @echo "Compiling $@"
    $(MAKE) -C program1 A=true

是否有更好的方法可以做到这一点?我不想等待program2和program3完成就可以开始program1a编译.

Is there a better way to do this? I would like to not have to wait for the program2 and program3 to finish in order to start program1a compilation.

推荐答案

未经测试(如果不行，请告诉我)，但是您可以执行以下操作:

Not tested (tell me if this does not work), but you could do something like this :

compileall: program1 program2 program3
    @echo "Compilation completed"

program1: program1a
    @echo "Compiling $@"
    $(MAKE) -C $@

program1a program2 program3:
    @echo "Compiling $@"
    $(MAKE) -C $@

那样，应该在program1之前先构建program1a，并且make应该能够同时并行构建program2和program3.

That way program1a should be built before program1 and make should be able to build program2 and program3 in parallel anyway.

编辑:更加简洁(谢谢@Beta):

EDIT: A little bit cleaner (thx @Beta):

compileall: program1 program2 program3
    @echo "Compilation completed"

program1: program1a

program1 program1a program2 program3:
    @echo "Compiling $@"
    $(MAKE) -C $@

---

编辑2 :我想到的避免依赖的唯一解决方案如下.

---

EDIT 2: The only solution that comes to my mind to avoid dependencies is as follow.

创建2个单独的makefile，如下所示:

Create 2 separate makefiles like this :

# Makefile1.mk

.NOTPARALLEL: # Force disabling of -j flag

all: program1 program1a

program1 program1a:
    @echo "Compiling $@"
    $(MAKE) -C $@

# Makefile

all: program1 program1a program2 program3

program1 program1a:
    $(MAKE) -f Makefile1.mk

program2 program3:
    @echo "Compiling $@"
    $(MAKE) -C $@

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