VHDL:是否可以用记录定义泛型? [英] VHDL: Is it possible to define a generic type with records?

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问题描述

我试图定义一个复杂的类型(即由实部和虚部组成的类型),并试图找到一种使之通用的方法.

I am trying to define a complex type (i.e, a type that consists of both a real and imaginary part) and am trying to find out a way to make it generic.

This my current static code:

  type complex_vector is record
    Re : signed(15 downto 0);
    Im : signed(15 downto 0);
  end record;

现在,我想知道是否有一种方法可以使这种通用名称,换句话说,像这样:

Now I wonder whether there is a way to make this generic, in in other word something like:

  type complex_vector (Generic: Integer := WIDTH) is record
    Re : signed(WIDTH downto 0);
    Im : signed(WIDTH downto 0);
  end record;

我尝试通过谷歌搜索解决方案以及阅读书籍,但找不到任何解决方案.真的没有吗?没有记录,可能会发生以下情况:

I tried to google for a solution as well as going through my books, but I cannot find any solution. Is there really none? Without records it is possible to wright something like this:

type blaaa is array (NATURAL range <>) of STD_LOGIC;

感谢您的任何输入

或者我可以做以下事情吗?

Or could I do something like the following?

type complex_primitives is (re, im);
type complex_vector is array (re to im) of signed(natural range <>);

编译器抱怨..

推荐答案

以下是VHDL-2008中的合法语法:

The following is legal syntax in VHDL-2008:

type complex is record
  re : signed ;  -- Note that this is unconstrained
  im : signed ;
end record ;

signal my_complex_signal : complex (re(7 downto 0), im(7 downto 0)) ;

重要说明本示例使用具有不受约束的数组的记录.这时对VHDL-2008的支持是一触即发的.一些工具支持VHDL-2008的许多功能,但是许多工具尚未完全支持所有新功能.

IMPORTANT NOTE This example makes use of records with unconstrained arrays. Support for VHDL-2008 at this point is hit-and-miss. Some tools support many of VHDL-2008 features, but many do not yet fully support all new features.

要了解有关VHDL-2008和新功能的信息,请参见此演示文稿关于这个问题的很好的总结.

To read about VHDL-2008 and the new features, see this presentation which is a good summary on the subject.

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