VHDL表达式不是常数 [英] VHDL expression is not constant

问题描述

我正在Quartus II上为CYCLONE III EP3C25 FPGA编写VHDL程序，但是遇到了问题.

I am writing a VHDL program on quartus II for a CYCLONE III EP3C25 FPGA and I got an issue.

这是我程序的重要部分:

Here are the important part of my program:

odata : out std_logic_vector(15 downto 0);

signal buf_data : std_logic_vector(255 downto 0);

signal nb_word : integer :=0;

Process(clk,RST)
begin
    if(RST='0') then
        nb_word<=0;
    elsif(clk'event and clk='0') then
        if(Current_state_w=s2) then
            if(nb_word<=X"F0") then
                nb_word<=nb_word+16;
            else
                nb_word<=0;
            end if;
        end if;
    end if;
end process;

Process(clk,RST)

begin
    if(RST='0') then
        odata<=(OTHERS=>'0');
    elsif(clk'event and clk='0') then
            odata<=buf_data(nb_word+15 downto nb_word);
    end if;
end process;

这段代码可以很好地编译，但是没有执行我想要的操作，然后我只想更改:

This code is compiling fine but does not do what I want then I just wanted to change :

odata<=buf_data(nb_word+15 downto nb_word);

在

odata<=buf_data(nb_word downto nb_word-15);

然后我将nb_word的初始化和重置值更改为15，而不是0.

And I changed the initialisation and reset value of nb_word at 15 instead of 0.

问题是，当我这样做并尝试编译时出现此错误:

The problem is, when I do that and I try compiling I got this error:

Error (10779): VHDL error at VL_control.vhd(99): expression is not constant

该行对应于odata行的更改.

The line corresponds to the changement of the odata line.

我真的不明白为什么会出现此错误.为什么可以加法而不是减法?我还试图定义另一个信号，并在对缓冲区进行寻址之前对信号进行减法运算:

I really can't understand why I got this error. Why is it possible to do an addition and not a substraction? I also tried to define another signal and to do the substraction in the signal before addressing the buffer like that:

nb_word1 := (nb_word-15);
odata<=buf_data(nb_word downto nb_word1);

但是我仍然遇到相同的错误.那是哪里来的?????

But I still get the same error. Where does that come from?????

推荐答案

您应该将 nb_word 限制为整数范围，这样合成工具才能确定 nb_word的值-15 不能为负.

You should limit nb_word to an integer range, that way the sythesis tool knows for sure that the value of nb_word - 15 can not be negative.

此外，为什么还要将整数与位字符串文字进行比较?为什么不说如果nb_word<15 ?

Also, why do you compare an integer to a bit string literal? Why not just say if nb_word < 15?

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