同花顺高速缓存DRAM [英] Flush cache to DRAM
问题描述
我使用赛灵思ZYNQ平台的可编程硬件和ARM处理器之间共享内存区域。
I'm using a Xilinx Zynq platform with a region of memory shared between the programmable HW and the ARM processor.
我保留使用内核命令行MEMMAP这个内存，然后它暴露在通过我的司机MMAP / io_remap_pfn_range调用用户空间。
I've reserved this memory using memmap on the kernel command line and then exposed it to userspace via mmap/io_remap_pfn_range calls in my driver.
我遇到的问题是，它需要一些时间写在DRAM中露面，我presume它停留在DCACHE。有一堆定义，但他们都不远销flush_cache_ *通话，这是一个线索，我认为我找错了树...
The problem I'm having is that it takes some time for the writes to show up in DRAM and I presume it's stuck in dcache. There's a bunch of flush_cache_* calls defined but none of them are exported, which is a clue to me that I'm barking up the wrong tree...
作为试验我在本地出口flush_cache_mm，只是看看会发生什么，并没有喜悦。
As a trial I locally exported flush_cache_mm and just to see what would happen and no joy.
总之，我怎么能确信这个mmap'd地区的任何写入操作一直致力于DRAM？
In short, how can I be sure that any writes to this mmap'd regions have been committed to DRAM?
感谢。
推荐答案
在 ARM 处理器通常既有的 I / D缓存的和的写缓冲的。一个的写入缓冲区的想法的是黑帮的顺序写入在一起（伟大的同步DRAM 的），并不会耽误CPU等待的写的来完成的。
The ARM processors typically have both a I/D cache and a write buffer. The idea of a write buffer is to gang sequential writes together (great for synchronous DRAM) and to not delay the CPU to wait for a write to complete.
要成为的通用的，你可以刷新的ð缓存的和的写缓冲的。以下是一些行内的 ARM 汇编程序应为工作很多的架构的和内存配置。
To be generic, you can flush the d cache and the write buffer. The following is some inline ARM assembler which should work for many architectures and memory configurations.
static inline void dcache_clean(void)
{
const int zero = 0;
/* clean entire D cache -> push to external memory. */
__asm volatile ("1: mrc p15, 0, r15, c7, c10, 3\n"
" bne 1b\n" ::: "cc");
/* drain the write buffer */
__asm volatile ("mcr 15, 0, %0, c7, c10, 4"::"r" (zero));
}
您可能需要更多，如果你有一个的二级缓存的
You may need more if you have an L2 cache.
要在Linux方面回答，也有不同的 CPU 根据内存/ MMU配置，甚至CPU勘误变型和不同的例程。例如，见
To answer in a Linux context, there are different CPU variants and different routines depending on memory/MMU configurations and even CPU errata. See for instance,
- proc-arm926.S
- cache-v7.S
- cache-v6.S
- etc
这些程序直接调用或在 CPU信息抬头的结构，函数指针，为检测CPU和配置相应的程序;这取决于内核是否为的单CPU 或多功能的像 Ubuntu发行版专用
These routines are either called directly or looked up in a cpu info structure with function pointers to the appropriate routine for the detected CPU and configuration; depending on whether the kernel is special purpose for a single CPU or multi-purpose like a Ubuntu distribution.
要明确回答这个问题为您的情况，我们需要知道的二级缓存的写缓冲的内存的 CPU架构的具体细节;也许包括硅版本的的勘误表的。另一个策略是完全通过避免这种情况的<一个href=\"https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/arch/arm/include/asm/dma-mapping.h\"><$c$c>dma_alloc_XXX()例程这标志着内存的未缓存的和的未缓冲的的使CPU写入由外部立即推。根据你的内存访问模式，任何一种解决方案是有效的。你不妨缓存，如果内存仅需要的同步的一些检查站（ VSYNC 的/ * * HSYNC视频等）。
To answer the question specifically for your situation, we need to know L2 cache, write buffered memory, CPU architecture specifics; maybe including silicon revisions for errata. Another tactic is to avoid this completely by using the dma_alloc_XXX() routines which mark memory as un-cacheable and un-bufferable so that the CPU writes are pushed externally immediately. Depending on your memory access pattern, either solution is valid. You may wish to cache if the memory only needs to be synchronized at some checkpoint (vsync/*hsync* for video, etc).
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