旋转左 verilog 大小写 [英] Rotate left verilog case

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本文介绍了旋转左 verilog 大小写的处理方法,对大家解决问题具有一定的参考价值,需要的朋友们下面随着小编来一起学习吧!

问题描述

我的任务是用 verilog 编写一个 16 位的 ALU.当我做需要旋转操作数的部分和做2的补码加减法时,我发现了困难.我知道如何用纸和铅笔解决这个问题,但我无法想出在 Verilog 中的方法.例如:A 表示为 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0如果我要旋转 4 位,答案是a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a15 a14 a13 a12

My task is to write a 16 bit ALU in verilog. I found difficulties when I do the part that needs to rotate the operand and doing the 2's complement addition and subtraction. I know how to work that out by paper and pencil but i cant figure out ways to do it in Verilog. for example: A is denoted as a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 if i am going to rotate 4 bits, the answer would be a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a15 a14 a13 a12

我尝试了连接,但结果是不正确的.需要大家的帮助...

i tried concatenation but it turns out to be incorrect. need you all help...

推荐答案

为什么串联不正确?这应该可以满足您的要求.

Why is concatenation incorrect? This should do what you ask.

 assign A_out[15:0] = {A_in[11:0], A_in[15:12]};

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