VHDL - 在 7 段显示器上滚动文本 [英] VHDL - Scrolling Text on 7 segment Display

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问题描述

我的项目即将结束,但在某些时候卡住了.我无法解决问题

I am near to end in my project but stuck at some point. I can not resolve the problem

在确定 VHDL 很难移动数组索引后,我决定更改我的移位器模块.现在它可以正确编译并且 RTL 原理图似乎是正确的,但不幸的是我使用了一种相当非创新的方式来移动扫描码.

After deciding VHDL is having a hard time shifting indexes of arrays, I decided to change my shifter module. Now it is properly compiling and the RTL schematic seems true, but unfortunately I used a rather non-innovative way to shift the scancodes.

我定义了一个最多可容纳 8 个扫描码的 64 位 std_logic_vector,然后解析该向量的 4 个 MSBmost 字节,并将它们定向到七段控制器,该控制器对输入进行多路复用并决定将启用哪七段.我想我的时钟有问题,但在显示屏上看不到任何东西让我认为设备的某些部分出现故障.我确信我的键盘控制器工作正常,因为我单独尝试过,移位器看起来也不错(我也在 FPGA 上尝试过这个,但没有减慢时钟,但我还是能够看到我输入的最后一个扫描码),我还没有想过尝试 7 段控制器的任何方式/方法,但这似乎也很好.我不知道问题是什么,文本没有滚动:(

I defined an 64bit std_logic_vector that can hold up to 8 scancodes, and then parsed the 4 MSBmost bytes of this vector, and directed them to seven segment controller, that muxes the inputs and decides which seven segment will be enabled. I am thinking that I have problems with clock, but seeing nothing on the display makes me think some part of the device is malfunctioning. I am sure my keyboard controller works fine, as I tried it outindividually, shifter looks fine as well( I also tried this one on FPGA but without slowing the clock down, but nevertheless I was able to see the last scancode I entered), I haven't thought of any way/method to try out 7 segment controller, but that seems fine too. I don't know what the problem is, the text is not scrolling :(

Shifter.vhd

Shifter.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;

entity my_shifter is
        port(clk      : in  std_logic;
                Scan_Dav : in  std_logic;
                Data_in  : in  std_logic_vector (7 downto 0);
                O1 : out std_logic_vector(7 downto 0);
                O2 : out std_logic_vector(7 downto 0);
                O3 : out std_logic_vector(7 downto 0);
                O4 : out std_logic_vector(7 downto 0)
                );
end my_shifter;

architecture bhv of my_shifter is

signal bytes : std_logic_vector(63 downto 0);
begin
    process (clk) begin
        if rising_edge(clk) then
                if Scan_Dav = '1' then
                    bytes <= bytes (bytes'high-8 downto 0) & Data_in;
                end if;
          end if;
    end process;
     O1 <= bytes(63 downto 56);
     O2 <= bytes(55 downto 48);
     O3 <= bytes(47 downto 40);
     O4 <= bytes(39 downto 32);
end bhv;

clkdivide.vhd

clkdivide.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clkdivide is
    Port (clkin: in std_logic;
            clkout:out std_logic );
end clkdivide;

architecture Behavioral of clkdivide is
    signal int_clock:std_logic;
    begin
        clkout<=int_clock;
    process(clkin)
        variable var:integer range 0 to 12500 :=0;
        begin
            if (clkin'event and clkin = '1') then
                if var = 12500 then
                    int_clock <= not int_clock; 
                    var:=0;
                else 
                    var:=var+1;
                end if;
            end if;
    end process;
end Behavioral;

SevenSegmentControl.vhd:

SevenSegmentControl.vhd:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity SevenSegmentController is
    port (
        CLK: in std_logic;
        DEC1, DEC2, DEC3, DEC4: in std_logic_vector(7 downto 0);
        SEGMENTS: out std_logic_vector(6 downto 0);
        ANODES: out std_logic_vector(3 downto 0)
    );
end SevenSegmentController;

architecture Behavioral of SevenSegmentController is
   signal DecoderInput: std_logic_vector(7 downto 0);
    signal CurrentDisplay: std_logic_vector(1 downto 0) := "00";
    signal Prescaler: std_logic_vector(15 downto 0) := (others => '0');
begin

    Multiplex: process(CLK)
    begin
        if rising_edge(CLK) then
            if Prescaler(15) = '0' then
                Prescaler <= Prescaler + 1;
            else
                CurrentDisplay <= CurrentDisplay + 1;
                Prescaler <= (others => '0');
            end if;
        end if;
    end process Multiplex;

    SevenSegmentDecoder: entity work.SevenSegment_Decoder(Behavioral)
        generic map ( INVERT_OUTPUT => '1' )
        port map ( number => DecoderInput, segment => SEGMENTS );   

    DecoderInput <= DEC1 when CurrentDisplay = "00" else
                        DEC2 when CurrentDisplay = "01" else
                         DEC3 when CurrentDisplay = "10" else
                         DEC4 when CurrentDisplay = "11";

   ANODES <= "0111" when CurrentDisplay = "00" else
                 "1011" when CurrentDisplay = "01" else
                 "1101" when CurrentDisplay = "10" else
                 "1110" when CurrentDisplay = "11";              

end Behavioral;

推荐答案

我还没有想出任何方式/方法来尝试7段控制器"

"I haven't thought of any way/method to try out 7 segment controller"

除非您使用的是非常旧的 ISE 版本,肯定比 ISE10 早,否则它内置了相当不错的模拟器 (ISIM).(ISIM 比 ISE10 更早,但它并不是真的可用,甚至 ISIM 10有它的问题...)

Unless you are using a VERY old version of ISE, certainly older than ISE10, it has a fairly decent simulator (ISIM) built in. (ISIM goes back further than ISE10, but it wasn't really usable and even ISIM 10 had its problems...)

如果您编写一个简单的测试平台并在进行过程中对这些模块进行单元测试,您将节省大量时间.

You would save a lot of time if you wrote a simple testbench and unit-tested these modules as you went along.

这篇关于VHDL - 在 7 段显示器上滚动文本的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!

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