在 VHDL 设计中什么时候使用块语句,什么时候不使用? [英] When do you use a block statement in a VHDL design and when do you not?

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问题描述

我来自软件世界,最近我开始在 VHDL 中创建 FPGA 设计.我已经阅读了 block 并发语句及其主要用途,例如组织架构,对并发代码和保护信号进行分组,这是不推荐的.

I come from SW world and recently I've started to create FPGA designs in VHDL. I've read about the block concurrent statement and its principal uses like organize architecture grouping concurrent code and guard signals, which is not recommendable.

但这是实现相同功能的众多可能性之一.例如,我已经实现了一个带有 VHDL 功能的 CRC 帧检查器.它有一位值输入,并返回一个寄存器,其中包含所有位输入的累积CRC值.

But this is one of many possibilities in order to implement the same functionality. For instance, I've been implemented a CRC frame checker with a VHDL function. It has one bit value input, and return a register with the cumulative CRC value of all bit inputs.

我认为可以用 block 实现相同的功能.资源利用的最佳选择是什么?你什么时候会使用 block ,什么时候不会?哪种情况最适合实现 block?

I think the same functionality can be implemented with a block. What is the best option for resource utilization? When would you use a block and when would not? Which is the best case to implement a block?

谢谢,

推荐答案

资源利用的最佳选择是什么?

有无block在资源利用上应该没有区别.这假设您正在创建相同的逻辑.

What is the best option for resource utilization?

There should be no different between with or without block in terms of resource utilization. This assumes that you're creating the same logic.

与软件类似,您想使用 block 语句的唯一原因是您想限制部分代码中使用的变量的范围.这可以在大型设计中显着提高代码可读性,其中信号可以在同一区域声明和使用.

Similar to software, the only reason you want to use block statement is when you want to limit the scope of the variables used within a portion of the code. This can significantly improve code readability in a large design where signals can be declared and utilized in the same region.

我不建议任何人在小型设计中使用 block 语句,或者在组件实例化更合适的地方使用.

I would not recommend anyone to use block statement in a small design, or where component instantiation is more appropriate.

当它提高代码可读性时.

When it improves code readability.

这篇关于在 VHDL 设计中什么时候使用块语句,什么时候不使用?的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!

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