网络的恒定驱动程序,vhdl shiftreg [英] constant drivers for net, vhdl shiftreg
问题描述
我正在尝试在 vhdl 中制作一个移位寄存器.
I'm trying to make a shiftregister in vhdl.
我的问题是当我尝试在注册表中存储值时.这是导致问题的代码:
My issue is when I try to store values in the regisgter. This is the code that's causing trouble:
architecture behave of chan_mod is
signal adc_shfreg : std_logic_vector(15 DOWNTO 0);
signal dac_shfreg : std_logic_vector(15 DOWNTO 0);
begin
Rcv_adc:
process(mclk, reset)
begin
if rising_edge(mclk) then
if (reset = '0') then
adc_out <= "0000000000000000";
elsif(chan_on = '1' AND subcycle_cntr = "01" AND chan_sel = '0' AND bit_cntr < 16) then
adc_shfreg <= adc_shfreg(14 DOWNTO 0) & adcdat;
end if;
end if;
end process;
adc_out <= adc_shfreg; --compilation error here
我得到的错误是:
错误 (10028):无法解析网络的多个常量驱动程序chan_mod.vhd(40) 处的adc_out[13]"
Error (10028): Can't resolve multiple constant drivers for net "adc_out[13]" at chan_mod.vhd(40)
不知道您是否需要查看我的端口,但它们在这里:
dont know if you need to see my ports, but here they are:
entity chan_mod is
Port ( mclk : in std_LOGIC;
reset : in std_logic;
chan_on : in std_logic;
chan_sel : in std_logic;
adcdat : in std_logic;
dacdat : out std_logic;
bit_cntr : in std_logic_vector(4 DOWNTO 0);
subcycle_cntr : in std_logic_vector(1 downto 0);
dac_in : in std_logic_vector(15 DOWNTO 0);
adc_out : out std_LOGIC_vector(15 DOWNTO 0);
rd : in std_logic;
wr : in std_logic);
end chan_mod;
(正如您可能猜到的,其中一些在代码后面使用,因此不在我的代码示例中)
(as you probably guessed a few of these are used later in the code and are therefore not in my code-sample)
推荐答案
您的问题是您在流程中驱动 adc_out 以及使用并发分配.您应该将重置情况下对 adc_out 的分配替换为对 adc_shfreg 的分配.
Your problem is that you're driving adc_out in the process as well as using a concurrent assignment. You should replace the assignment to adc_out in the reset case with an assignment to adc_shfreg.
architecture behave of chan_mod is
signal adc_shfreg : std_logic_vector(15 DOWNTO 0);
signal dac_shfreg : std_logic_vector(15 DOWNTO 0);
begin
Rcv_adc:
process(mclk, reset)
begin
if rising_edge(mclk) then
if (reset = '0') then
adc_out <= "0000000000000000"; <--- BAD! Replace adc_out with adc_shfreg
elsif(chan_on = '1' AND subcycle_cntr = "01" AND chan_sel = '0' AND bit_cntr < 16) then
adc_shfreg <= adc_shfreg(14 DOWNTO 0) & adcdat;
end if;
end if;
end process;
adc_out <= adc_shfreg; --compilation error here
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