将缓存刷新到 DRAM [英] Flush cache to DRAM
问题描述
我使用的是 Xilinx Zynq 平台，其中一个内存区域在可编程硬件和 ARM 处理器之间共享.
I'm using a Xilinx Zynq platform with a region of memory shared between the programmable HW and the ARM processor.
我在内核命令行上使用 memmap 保留了这个内存，然后通过我的驱动程序中的 mmap/io_remap_pfn_range 调用将它暴露给用户空间.
I've reserved this memory using memmap on the kernel command line and then exposed it to userspace via mmap/io_remap_pfn_range calls in my driver.
我遇到的问题是写入内容需要一些时间才能显示在 DRAM 中，而且我认为它卡在了 dcache 中.定义了一堆 flush_cache_* 调用，但没有一个被导出，这对我来说是一个线索，我正在吠叫错误的树......
The problem I'm having is that it takes some time for the writes to show up in DRAM and I presume it's stuck in dcache. There's a bunch of flush_cache_* calls defined but none of them are exported, which is a clue to me that I'm barking up the wrong tree...
作为试验，我在本地导出了flush_cache_mm，只是想看看会发生什么，但并不高兴.
As a trial I locally exported flush_cache_mm and just to see what would happen and no joy.
简而言之，我如何确定对此 mmap 区域的任何写入都已提交到 DRAM?
In short, how can I be sure that any writes to this mmap'd regions have been committed to DRAM?
谢谢.
推荐答案
ARM 处理器通常同时具有 I/D 缓存 和 写入缓冲区.写入缓冲区的想法是将顺序写入组合在一起(非常适合同步 DRAM)，并且不会延迟 CPU 等待 写入完成.
The ARM processors typically have both a I/D cache and a write buffer. The idea of a write buffer is to gang sequential writes together (great for synchronous DRAM) and to not delay the CPU to wait for a write to complete.
要成为通用，您可以刷新d 缓存和写入缓冲区.以下是一些内联 ARM 汇编程序，它应该适用于许多架构和内存配置.
To be generic, you can flush the d cache and the write buffer. The following is some inline ARM assembler which should work for many architectures and memory configurations.
static inline void dcache_clean(void)
{
const int zero = 0;
/* clean entire D cache -> push to external memory. */
__asm volatile ("1: mrc p15, 0, r15, c7, c10, 3\n"
" bne 1b\n" ::: "cc");
/* drain the write buffer */
__asm volatile ("mcr 15, 0, %0, c7, c10, 4"::"r" (zero));
}
如果您有 L2 缓存，您可能需要更多.
You may need more if you have an L2 cache.
要在 Linux 上下文中回答，根据内存/MMU 配置甚至 CPU 勘误表，有不同的 CPU 变体和不同的例程.参见例如，
To answer in a Linux context, there are different CPU variants and different routines depending on memory/MMU configurations and even CPU errata. See for instance,
这些例程要么被直接调用，要么在 cpu info 结构中查找，并带有指向检测到的 CPU 和配置的适当例程的函数指针；取决于内核是针对单个 CPU 的特殊用途还是多用途，例如 Ubuntu 发行版.
These routines are either called directly or looked up in a cpu info structure with function pointers to the appropriate routine for the detected CPU and configuration; depending on whether the kernel is special purpose for a single CPU or multi-purpose like a Ubuntu distribution.
要专门针对您的情况回答问题，我们需要了解L2 缓存、写缓冲 内存、CPU 架构 细节；可能包括勘误的硅修订版.另一种策略是通过使用 dma_alloc_XXX() 例程 将内存标记为 un-cacheable 和 un-bufferable 以便CPU 写入会立即从外部推送.根据您的内存访问模式，任一解决方案都有效.如果内存只需要在某个检查点同步(vsync/*hsync* 用于视频等)，您可能希望缓存.
To answer the question specifically for your situation, we need to know L2 cache, write buffered memory, CPU architecture specifics; maybe including silicon revisions for errata. Another tactic is to avoid this completely by using the dma_alloc_XXX() routines which mark memory as un-cacheable and un-bufferable so that the CPU writes are pushed externally immediately. Depending on your memory access pattern, either solution is valid. You may wish to cache if the memory only needs to be synchronized at some checkpoint (vsync/*hsync* for video, etc).
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