双核处理器究竟是什么? [英] What exactly is a dual-issue processor?

问题描述

我曾多次提到双问题处理器的概念(我希望这甚至可以在句子中说得通).我找不到任何关于双重问题究竟是什么的解释.谷歌给了我微控制器规范的链接，但这个概念没有在任何地方解释.以下是此类参考的示例.我找错地方了吗?简要说明它是什么会非常有帮助.

I came across several references to the concept of a dual issue processor (I hope this even makes sense in a sentence). I can't find any explanation of what exactly dual issue is. Google gives me links to micro-controller specification, but the concept isn't explained anywhere. Here's an example of such reference. Am I looking in the wrong place? A brief paragraph on what it is would be very helpful.

推荐答案

双重问题意味着每个时钟周期处理器可以将两条指令从流水线的一个阶段移动到另一个阶段.发生这种情况的地方取决于处理器和公司的术语:这可能意味着两条指令从解码队列移动到重新排序队列(英特尔称此问题)，或者可能意味着从一个移动指令(或微操作或其他东西)将队列重新排序到执行端口(IBM 称之为此问题，而 Intel 称之为调度)

Dual issue means that each clock cycle the processor can move two instructions from one stage of the pipeline to another. Where this happens depends on the processor and the company's terminology: it can mean that two instructions are moved from a decode queue to a reordering queue (Intel calls this issue) or it could mean moving instructions (or micro-operations or something) from a reordering queue to an execution port (afaik IBM calls this issue, while Intel calls it dispatch)

但从广义上讲，它通常意味着您可以维持每个周期执行两条指令.

But really broadly speaking it should usually mean you can sustain executing two instructions per cycle.

既然你标记了这个 ARM，我认为他们使用的是英特尔的术语.Cortex-A8 和 Cortex-A9 可以在每个周期获取两条指令(在 Thumb-2 中更多)，解码两条指令，并发出"两条指令.在 Cortex-A8 上，没有乱序执行，虽然我不记得是否还有一个解码队列你发出 - 如果没有，你会直接从解码指令到将它们插入到两个执行管道中.在 Cortex-A9 上有一个发出队列，所以解码后的指令在那里发出 - 然后指令以每个周期最多 4 个分派到执行管道.

Since you tagged this ARM, I think they're using Intel's terminology. Cortex-A8 and Cortex-A9 can, each cycle, fetch two instructions (more in Thumb-2), decode two instructions, and "issue" two instructions. On Cortex-A8 there's no out of order execution, although I can't remember if there's still a decode queue that you issue to - if not you'd go straight from decoding instructions to inserting them into two execution pipelines. On Cortex-A9 there's an issue queue, so the decoded instructions are issued there - then the instructions are dispatched at up to 4 per cycle to the execution pipelines.

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