带有 GIC 的 SMP ARM 系统上的中断处理 [英] Interrupt handling on an SMP ARM system with a GIC

问题描述

我想知道从任何设备被中断的那一刻起中断处理是如何工作的.我知道点点滴滴的中断处理，并且想要清楚地了解中断处理的端到端图片.让我把我所知道的一点点介绍一下关于中断处理.

I wanted to know how interrupt handling works from the point any device is interrupted.I know of interrupt handling in bits and pieces and would like to have clear end to end picture of interrupt handing.Let me put across what little I know about interrupt handling.

假设 FPGA 设备通过电线中断并获取一些数据.该 FPGA 设备的设备驱动程序已经使用 request_irq 函数注册了代码(中断处理程序).

Suppose an FPGA device is interrupted through electrical lines and get some data .Device driver for this FPGA device already had code (Interrupt handler) registered using request_irq function.

所以现在 FPGA 设备有一个 IRQ 线，它在调用 request_irq 之后，使用这个 IRQ 线设备将数据发送到通用中断控制器，GIC 将对 IRQ 线进行多对一转换并将信号发送到 CPU 内核然后调用下面的最小代码

So now FPGA device have an IRQ line which it get after to call request_irq ,using this IRQ line device send data to the General Interrupt controller and GIC will do many to one translation of IRQ lines and send the signal to CPU core which then call below minimal code

IRQ_handler
SUB       lr, lr, #4       ; modify LR
SRSFD     #0x12!           ; store SPSR and LR to IRQ mode stack
PUSH      {r0-r3, r12}     ; store AAPCS registers on to the IRQ mode stack
BL        IRQ_handler_to_specific_device
POP       {r0-r3, r12}     ; restore registers
RFEFD     sp!              ; and return from the exception using pre-modified LR 

IRQ_handler_to_specific_device 是我们使用 request_irq() 调用在设备驱动程序中注册的内容.

IRQ_handler_to_specific_device is nothing is what we registered in Device driver using request_irq() call.

我还是不明白CPU核心是如何知道中断源的?(来自哪个设备中断)

I still don't how CPU core comes to know about the interrupt source?(from which device interrupt is coming)

还有像 do_irq 这样的调用和共享中断的作用是什么?

Also what is role of call like do_irq and shared interrupts works?

在理解 ARM 架构上如何处理中断的端到端图片方面需要一些帮助吗?

Need some help in understanding end to end picture on how interrupts are handled on ARM architecture?

推荐答案

GIC 分为两个部分.第一个称为分销商.这对系统来说是全局的.它有几个物理路由到它的中断源；尽管它可能在 SOC 封装中.第二部分是按 CPU 复制的，它称为 cpu 接口.分发器具有关于如何分发共享外设中断或SPI的逻辑.这些是您的问题所询问的中断类型.它们是全局硬件中断.

The GIC is divided into two sections. The first is called the distributor. This is global to the system. It has several interrupt sources physically routed to it; although it maybe within an SOC package. The second section is replicated per-CPU and it called the cpu interface. The distributor has logic on how to distribute the shared peripheral interrupts or SPI. These are the type of interrupt your question is asking about. They are global hardware interrupts.

在Linux环境下，这是在irq-gic.c.gic.txt.特别感兴趣，

In the context of Linux, this is implemented in irq-gic.c. There is some documentation in gic.txt. Of specific interest,

• reg :指定 GIC 寄存器的基本物理地址和大小.这第一个区域是 GIC 分销商 注册基础和规模.第二个区域是GIC cpu 接口寄存器基数和大小.

• reg : Specifies base physical address(s) and size of the GIC registers. The first region is the GIC distributor register base and size. The 2nd region is the GIC cpu interface register base and size.

distributor 必须全局访问，因此必须小心管理它的寄存器.CPU 接口对于每个 CPU 具有相同的物理地址，但每个 CPU 都有单独的实现.分配器可以设置为将中断路由到特定的 CPU(包括多个).参见:gic_set_affinity() 例如.任何 CPU 也可以处理中断.ACK 寄存器将分配 IRQ；第一个读取它的 CPU 获得中断.如果有多个 IRQ 挂起，并且有来自不同 CPU 的两次 ACK 读取，那么每个都会得到不同的中断.第三次 CPU 读取会得到 虚假 IRQ.

The distributor must be accessed globally, so care must be taken to manage it's registers. The CPU interface has the same physical address for each CPU, but each CPU has a separate implementation. The distributor can be set up to route interrupts to specific CPUs (including multiples). See: gic_set_affinity() for example. It is also possible for any CPU to handle the interrupt. The ACK register will allocate IRQ; the first CPU to read it, gets the interrupt. If multiple IRQs pend and there are two ACK reads from different CPUs, then each will get a different interrupt. A third CPU reading would get a spurious IRQ.

同样，每个 CPU 接口都有一些私有中断源，用于 CPU 到 CPU 的中断以及私有定时器等.但我认为问题的重点是物理外设(系统独有)如何路由到 SMP 系统中的 CPU.

As well, each CPU interface has some private interrupt sources, that are used for CPU-to-CPU interrupts as well as private timers and the like. But I believe the focus of the question is how a physical peripheral (unique to a system) gets routed to a CPU in an SMP system.

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