QWORD 在 64 位机器上的大小是多少? [英] What's the size of a QWORD on a 64-bit machine?

问题描述

我目前正在寻找上述问题的答案.到目前为止，我发现有人说，字长是指处理器寄存器的大小，这表明在 64 位机器上，字长是 64 位，因此 QWORD(4 * 字)的大小是 256 位.

I'm currently looking to find an answer to the above question. So far I found people saying, that the word size refers to the size of a processor register, which would suggest on a 64-bit machine the word size being 64 bits and thus a QWORD (4 * word) being 256 bits in size.

但另一方面，我发现了诸如 这 表示大小为 128 位(32 位为 64 位，64 位为两倍)，而即使如此，其他人建议大小为 64 位.但最后一个与 Microsoft 有某种关系，它通过将单词的大小定义为 16 位来混淆每个人，从而使事情变得更糟.

But on the other hand I found sources like this saying the size would be 128 bits (64 bits for 32-bit and doubled this for 64-bit), while even then others suggest the size would be 64 bits. But the last one is somehow related to Microsoft making matters worse by confusing everyone by defining the size of a word being 16 bits.

也许有人可以解决我的困惑并在这个主题上启发我.

Maybe someone could solve my confusion and enlighten me on this topic.

推荐答案

在 x86 术语/文档中，一个词"是 16 位，因为 x86 是从 16 位 8086 演变而来的.在添加扩展时更改术语的含义只会令人困惑，因为英特尔仍然必须记录 16 位模式和所有内容，以及指令助记符，例如cwd(将字符号扩展为双字)将术语放入 ISA.

In x86 terminology/documentation, a "word" is 16 bits because x86 evolved out of 16-bit 8086. Changing the meaning of the term as extensions were added would have just been confusing, because Intel still had to document 16-bit mode and everything, and instruction mnemonics like cwd (sign-extend word to dword) bake the terminology into the ISA.

• x86 字 = 2 个字节
• x86 双字 = 4 字节(双字)
• x86 qword = 8 字节(四字)
• x86 double-quad 或 xmmword = 16 字节，例如movdqa xmm0, [rdi].
  同样在 cqo 助记符中，oct-word.(将 RAX 符号扩展为 RDX:RAX，例如在 idiv 之前)

• x86 word = 2 bytes
• x86 dword = 4 bytes (double word)
• x86 qword = 8 bytes (quad word)
• x86 double-quad or xmmword = 16 bytes, e.g. movdqa xmm0, [rdi].
  Also in the cqo mnemonic, oct-word. (Sign-extend RAX into RDX:RAX, e.g. before idiv)

然后我们有有趣的指令，例如 punpcklqdq:将两个 qwords 混洗成一个 dqword，或 pclmulqdq 用于 qwords 的无进位乘法，产生 dq 完整结果.但除此之外，SIMD 助记符往往是 AVX vextracti128 或 AVX512(带有可选的每个元素屏蔽)vextractf64x4 提取 ZMM 寄存器的高 256 位.

And then we have fun instruction like punpcklqdq: shuffle together two qwords into a dqword, or pclmulqdq for carry-less multiplication of qwords, producing a dq full result. But beyond that, SIMD mnemonics tend to be AVX vextracti128 or AVX512 (with optional per-element masking) vextractf64x4 to extract the high 256 bits of a ZMM register.

更不用说像tbyte"这样的东西了= 10 字节 x87 扩展精度浮点数；x86 很奇怪，并不是所有的东西都是 2 的幂.还有保护模式下的 48 位 seg:off 16:32 远指针.(基本没用过，只是 32 位偏移部分.)

Not to mention stuff like "tbyte" = 10 byte x87 extended-precision float; x86 is weird and not everything is a power of 2. Also 48-bit seg:off 16:32 far pointers in Protected mode. (Basically never used, just the 32-bit offset part.)

大多数其他 64 位 ISA 都是从 32 位 ISA 演化而来的(AArch64、MIPS64、PowerPC64 等)，或者从一开始就是 64 位(Alpha)，所以词"在这种情况下表示 32 位.

Most other 64-bit ISAs evolved out of 32-bit ISAs (AArch64, MIPS64, PowerPC64, etc.), or were 64-bit from the start (Alpha), so "word" means 32 bits in that context.

• 32 位字 = 4 个字节
• dword = 8 字节(双字)，例如MIPS daddu 是 64 位整数加法
• qword = 16 字节(四字)，如果支持的话.

• 32-bit word = 4 bytes
• dword = 8 bytes (double word), e.g. MIPS daddu is 64-bit integer add
• qword = 16 bytes (quad word), if supported at all.

机器词"的整个概念并不真正适用于 x86，它的机器代码格式是字节流，并且对多个操作数大小的同等支持，以及大多数不关心自然对齐内容的未对齐加载/存储，只缓存普通可缓存内存的行边界.

The whole concept of "machine word" doesn't really apply to x86, with its machine-code format being a byte stream, and equal support for multiple operand-sizes, and unaligned loads/stores that mostly don't care about naturally aligned stuff, only cache line boundaries for normal cacheable memory.

即使是面向文字的"RISC 的寄存器和缓存访问的自然大小与其指令宽度或其文档用作字"的宽度不同.

Even "word oriented" RISCs can have a different natural size for registers and cache accesses than their instruction width, or what their documentation uses as a "word".

字长"的整个概念总体上被高估了，不仅仅是在 x86 上.即使是 64 位 RISC ISA 也可以以相同的效率加载/存储对齐的 32 位或 64 位内存，因此请选择对您正在做的事情最有用的那个.不要基于确定哪一个是机器的字长"来做出选择，除非只有一种最大有效的大小(例如，某些 32 位 RISC 上的 32 位)，那么您可以有用地将其称为字长.

The whole concept of "word size" is over-rated in general, not just on x86. Even 64-bit RISC ISAs can load/store aligned 32-bit or 64-bit memory with equal efficiency, so pick whichever is most useful for what you're doing. Don't base your choice on figuring out which one is the machine's "word size", unless there's only one maximally efficient size (e.g. 32-bit on some 32-bit RISCs), then you can usefully call that the word size.

一个词"并不意味着我听说过的任何 64 位机器上的 64 位.即使是从头开始设计为积极的 64 位的 DEC Alpha AXP，也使用 32 位指令字.IIRC，手册称一个字为 32 位位.

A "word" doesn't mean 64 bits on any 64-bit machine I've heard of. Even DEC Alpha AXP, which was designed from the ground up to be aggressively 64-bit, uses 32-bit instruction words. IIRC, the manual calls a word 32-bit bits.

能够用一条指令将 64 位加载到一个整数寄存器中，这并不意味着字长".位数和字长没有硬性的特定技术含义；大多数 CPU 内部有多种不同的大小.(例如，自 Haswell 以来，英特尔上 L2 和 L1d 缓存之间的 64 字节 总线，以及 32 字节的 SIMD 加载/存储.)

Being able to load 64-bits into an integer register with a single instruction does not make that the "word size". Bitness and word size don't have hard specific technical meanings; most CPUs have multiple different sizes internally. (e.g. 64 byte buses between L2 and L1d cache on Intel since Haswell, along with 32-byte SIMD load/store.)

所以基本上由 CPU 供应商的文档作者来选择什么词"(因此 dword/qword)表示他们的 ISA.

So it's basically up to the CPU vendor's documentation authors to choose what "word" (and thus dword / qword) mean for their ISA.

趣闻:SPARC64 谈到短词"；(32 位)与长字"(64 位)，而不是字/双字.我不知道是否只是词"没有任何限定符在 64 位 SPARC 文档中具有任何意义.

Fun fact: SPARC64 talks about "short word" (32 bits) vs. "long word" (64 bits), rather than word / double-word. I don't know if just "word" without any qualifier has any meaning in 64-bit SPARC documentation.

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