对准高速缓存行,并知道高速缓存行大小 [英] Aligning to cache line and knowing the cache line size

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问题描述

要prevent假共享,我想一个数组中的每个元素对齐高速缓存行。所以首先我需要知道的高速缓存行的大小,所以我分配每个元素的字节量。其次我想数组的开始到对齐的高速缓存行。

To prevent false sharing, I want to align each element of an array to a cache line. So first I need to know the size of a cache line, so I assign each element that amount of bytes. Secondly I want the start of the array to be aligned to a cache line.

我使用Linux和8核x86平台。首先我怎么找到的高速缓存行的大小。其次,我怎么对准C中的高速缓存行我使用gcc编译器。

I am using Linux and 8-core x86 platform. First how do I find the cache line size. Secondly, how do I align to a cache line in C. I am using the gcc compiler.

因此​​,结构将以下,例如,假设64的高速缓存行的大小。

So the structure would be following for example, assuming a cache line size of 64.

element[0] occupies bytes 0-63
element[1] occupies bytes 64-127
element[2] occupies bytes 128-191

和等,假定道即0-63对齐的高速缓存行。

and so on, assuming of-course that 0-63 is aligned to a cache line.

推荐答案

要知道尺寸,你需要看看它使用的文​​档处理器,据我所知是没有程序化的方式来做到这一点。在加方然而,大多数的高速缓存线是标准尺寸的,基于英特尔的标准。在x86高速缓存行64字节,然而,prevent假共享,您需要按照你的目标(英特尔在它的NetBurst架构的处理器提供一些特殊的注意事项)处理器的指导,一般需要调整到64字节为这个(英特尔的状态,你也应该避免穿越16字节边界值)。

To know the sizes, you need to look it up using the documentation for the processor, afaik there is no programatic way to do it. On the plus side however, most cache lines are of a standard size, based on intels standards. On x86 cache lines are 64 bytes, however, to prevent false sharing, you need to follow the guidelines of the processor you are targeting (intel has some special notes on its netburst based processors), generally you need to align to 64 bytes for this (intel states that you should also avoid crossing 16 byte boundries).

要在C或C这样做++,您需要使用 aligned_malloc 或编译器的具体说明符,如 __属性__((调整中的一个(64) )) __ declspec(调整(64))。要在结构成员之间垫它们分割到不同的高速缓存行,你需要插入足够大的成员,将其调整到下一个64字节的boundery

To do this in C or C++ requires that you use aligned_malloc or one of the compiler specific specifiers such as __attribute__((align(64))) or __declspec(align(64)). To pad between members in a struct to split them onto different cache lines, you need on insert a member big enough to align it to the next 64 byte boundery

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