makefile条件 [英] makefile conditionals

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问题描述

注意:使用MinGW的make(应该是GNU make)

Note: using MinGW's make (should be GNU make)

我有几个 -include 语句在我的makefile中导入使用 g ++ -MM 生成的依赖项。但是我想在必要时才这样做。我有几个不同的构建目标,我不希望包含所有相应的依赖文件,因为这需要一段时间(假设我正在运行 make clean :不需要在这种情况下包括它们)

i have a couple of -include statements in my makefile to import dependencies which were generated using g++ -MM. However I would like to only do this when necessary. I have several different build targets and I don't want all of their respective dependency files to be included since this takes a while (suppose I'm running make clean: no need to include them in this case)

这是我的makefile的格式。

Here's the format of my makefile.

DEPS_debug = $(patsubst %.cpp,build_debug/%.d,$(SRC))
OBJ_debug = $(patsubst %.cpp,build_debug/%.o,$(SRC))
all: program_debug
    -include $(DEPS_debug) #make: include: Command not found
program_debug: $(OBJ_debug)
    $(CC) $(CFLAGS) $(OBJ_debug) -o $@


推荐答案

如果你真的不想不必要地包含这些文件,你有几个选择:

If you really don't want to include those files needlessly, you have a couple of options:

你可以把有条件的迭戈塞维利亚建议(但我建议使用 MAKECMDGOALS ,以便你可以编写一个更灵活的版本,特定于目标,例如你将包括 foo.d 当且仅当你正在制作 foo.o )时。

You can put in a conditional as Diego Sevilla suggests (but I would recommend using MAKECMDGOALS so that you can write a more flexible version, specific to targets, e.g. you'll include foo.d if and only if you're making foo.o).

你可以使用make recursively(异端!),为每个目标对象调用 $(MAKE),使用包含该目标依赖项的makefile。

You can use make recursively (heresy!), invoking $(MAKE) for each target object, using a makefile that includes that target's dependencies.

但实际上包括文件需要忽略有时间,这是文件的重建(对任何包含过期的文件都是自动的)需要时间。
如果你想避免不必要的重建,你可以使用非常聪明的技巧。何时必须重建 foo.d ?只有当 foo 的内容发生了变化时。但在这种情况下,还必须重建 foo.o 。因此,对于 foo.d 没有单独的规则,只需将其重建为产生 foo.o 。这样你可以包含所有依赖文件,如果不需要,可以不浪费时间重建它们。

But actually including the file takes negligible time, it's the rebuilding of the file (automatic for any included file that's out of date) that takes time. If needless rebuilding is what you want to avoid, you can use a very clever trick. When must foo.d be rebuilt? Only when something about foo has changed. But in that case foo.o must also be rebuilt. So don't have a seperate rule for foo.d, just rebuild it as a side effect of making foo.o. That way you can include all dependency files and not waste time rebuilding them if they aren't needed.

编辑:

我很惊讶只有包括这些文件可以在 make clean 中添加2-3秒。我的最后一段是不合适的,所以让我扩展前两个选项。


I'm astounded that merely including these files can add 2-3 seconds to make clean. My last paragraph is off the mark, so let me expand on the first two options.

如果所有是只应包含这些文件的目标,并且你从命令行 make all (而不是例如 make all tests tarball install kitchenSink ),然后就可以了:

If all is the only target for which these files should be included, and you make all from the command line (and not e.g. make all tests tarball install kitchenSink), then this will do it:

ifeq ($(MAKECMDGOALS),all)
-include $(DEPS_debug)
endif

请注意,这将 include foo.d 如果你 make foo.o 。您可以编写更复杂的条件,例如

Note that this will not include foo.d if you make foo.o. You can write a more sophisticated conditional, something like

$(foreach targ,$(MAKECMDGOALS),$(eval $(call include_deps $(targ)))...

但这非常先进,所以让我们来看一个简单的版本先工作。

but that's pretty advanced, so let's get a simple version working first.

如果你宁愿避免使用条件并使用递归Make,最简单的方法是将makefile分成两部分:

If you'd rather avoid the conditional and use recursive Make, the simplest way is to split the makefile in two:

makefile:

all:
    $(MAKE) -f makefile.all

clean:
    rm whatever

...other rules

makefile.all:

makefile.all:

DEPS_debug = $(patsubst %.cpp,build_debug/%.d,$(SRC))
OBJ_debug = $(patsubst %.cpp,build_debug/%.o,$(SRC))
-include $(DEPS_debug)

all: program_debug
program_debug: $(OBJ_debug)
    $(CC) $(CFLAGS) $(OBJ_debug) -o $@

这篇关于makefile条件的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!

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