去抖状态图FSM [英] debounce state diagram FSM
问题描述
我正在使用有限状态机设计去抖滤波器。 FSM
的行为是它遵循初始输入位并且认为'真实的
输出直到它接收3个相同的位并且它改变输出
连续3位，直到收到接下来的3个连续位。
重置会将FSM设置为输出1s，直到它收到正确的输入和输出正确的
。
这是输入和输出正确的测试序列。
1 0 0 1 0 1 0 0 0 1 0 1 1 1（输入）
1 1 1 1 1 1 1 1 0 0 0 0 0 1（输出）
我出现的状态图有6个状态's SEE1，SEE11，
SEE111，SEE0，SEE00，SEE000。我在第11位陷入困境，输入为
的0。因为它刚刚来自SEE1，而且在SEE1之前，它来自SEE000，因此在SEE1，它无法将输出更改为1，这就是我指示该状态的
的输出是。
任何人都知道如何解决这个问题？或者也许还有其他更好的方法来设计状态图？
谢谢，
安森
我的建议：
将输入输入3位移位寄存器。
检测全1（111）并使用该信号设置锁存器，
检测全零（000）并使用该信号重置锁存器。
闩锁是你的反弹信号。
Peter Alfke
4月29日上午11点32分，Anson.Stugg ... @ gmail.com写道：
我正在使用有限状态机设计去抖滤波器。 FSM
的行为是它遵循初始输入位并且认为'真实的
输出直到它接收3个相同的位并且它改变输出
连续3位，直到收到接下来的3个连续位。
重置会将FSM设置为输出1s，直到它收到正确的输入和输出正确的
。
这是输入和输出正确的测试序列。
1 0 0 1 0 1 0 0 0 1 0 1 1 1（输入）
1 1 1 1 1 1 1 1 0 0 0 0 0 1（输出）
我出现的状态图有6个状态's SEE1，SEE11，
SEE111，SEE0，SEE00，SEE000。我在第11位陷入困境，输入为
的0。因为它刚刚来自SEE1，而且在SEE1之前，它来自SEE000，因此在SEE1，它无法将输出更改为1，这就是我指示该状态的
的输出是。
任何人都知道如何解决这个问题？或者也许还有其他更好的方法来设计状态图？
谢谢，
安森
4月29日上午11点45分，Peter Alfke< a ... @ sbcglobal.netwrote：
< blockquote class =post_quotes>
我的建议：
将输入输入3位移位寄存器。
检测全1（111）并使用设置锁存器的信号，
检测全零（000）并使用该信号重置锁存器。
锁存器是你的反弹信号。 />
Peter Alfke
4月29日上午11点32分，Anson.Stugg ... @ gmail.com写道：
我正在使用有限状态机设计adebouncefilter。 TheFSM
的行为是它跟在初始输入位之后，并认为'真实的
输出，直到它收到3个连续相同的位并且它改变输出
连续3位直到接收到接下来的3个连续位。
重置会将FSM设置为输出1s，直到它收到正确的
输入和输出。
这是输入和输出正确的测试序列。
1 0 0 1 0 1 0 0 0 1 0 1 1 1（输入）
1 1 1 1 1 1 1 1 0 0 0 0 0 1（输出）
我出现的状态图有6个状态，它的名字是SEE1，SEE11 ，
SEE111，SEE0，SEE00，SEE000。我在第11位陷入困境，输入为
的0。因为它刚刚来自SEE1，而且在SEE1之前，它来自SEE000，因此在SEE1，它无法将输出更改为1，这就是我指示该状态的
的输出是。
任何人都知道如何解决这个问题？或者也许还有其他更好的方法来设计状态图？
谢谢，
Anson-隐藏引用的文字 -
- 显示引用的文字 -
感谢Peter的建议。但我的问题是提出这个FSM的
状态图。我怎样才能实现你在
状态图上的建议？谢谢。
安森
一个************ @ gmail.com 写道：
I我正在使用有限状态机设计去抖滤波器。 FSM
的行为是它遵循初始输入位并且认为'真实的
输出直到它接收3个相同的位并且它改变输出
连续3位，直到收到接下来的3个连续位。
重置会将FSM设置为输出1s，直到它收到正确的输入和输出正确的
。
这是输入和输出正确的测试序列。
1 0 0 1 0 1 0 0 0 1 0 1 1 1（输入）
1 1 1 1 1 1 1 1 0 0 0 0 0 1（输出）
我出现的状态图有6个状态's SEE1，SEE11，
SEE111，SEE0，SEE00，SEE000。我在第11位陷入困境，输入为
的0。因为它刚刚来自SEE1，而且在SEE1之前，它来自SEE000，因此在SEE1，它无法将输出更改为1，这就是我指示该状态的
的输出是。
任何人都知道如何解决这个问题？或者也许还有其他更好的方法来设计状态图？
我不确定我理解你的术语，但我是
假设那个状态neames意味着：
SEE1 =输出= 0后连续1次输入。
SEE11 =输出= 0连续输入1次后连续2次。
SEE111 =连续3次输入1后输出= 1
（输入0后输入小于3时输入1
连续两次）。
SEE0 =连续1次输入0后输出= 1。
SEE00 =连续2次输入0后输出= 1
SEE000 =输出= 0连续3次输入后
（连续1次输入后输入0小于3
次）。
如果是这种情况，然后12个转换是：
之后输入
SEE1 1 SEE11
SEE1 0 SEE000
SEE11 1 SEE111
SEE11 0 SEE000
SEE111 1 SEE111
SEE111 0 SEE0
SEE0 1 SEE111
SEE0 0 SEE00
SEE00 1 SEE111
SEE00 0 SEE000
SEE000 1 SEE1
SEE000 0 SEE000
I''m designing a debounce filter using Finite State Machine. The FSM
behavior is it follows the inital input bit and thinks that''s real
output until it receives 3 consecutive same bits and it changes output
to that 3 consecutive bit until next 3 consecutive bits are received.
A reset will set the FSM to output 1s until it receives the correct
input and ouput.
This is the test sequence with input and correct output.
1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input)
1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output)
The state diagram I came up has 6 states and it''s named SEE1, SEE11,
SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in
the input. Because it just came from SEE1 and before SEE1, it came
from SEE000, so at SEE1 it can not change ouput to 1 which is what I
have specified that state''s ouput to be.
Anyone knows how to solve this problem? Or maybe there''s other better
ways to design the state diagram?
Thanks,
Anson
My suggestion:
Feed the input into a 3-bit shift register.
Detect all-ones (111) and used that signal to set a latch,
detect all-zeros (000) and use that signal to reset a latch.
The latch is your de-bounced signal.
Peter Alfke
On Apr 29, 11:32 am, Anson.Stugg...@gmail.com wrote:I''m designing a debounce filter using Finite State Machine. The FSM
behavior is it follows the inital input bit and thinks that''s real
output until it receives 3 consecutive same bits and it changes output
to that 3 consecutive bit until next 3 consecutive bits are received.
A reset will set the FSM to output 1s until it receives the correct
input and ouput.
This is the test sequence with input and correct output.
1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input)
1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output)
The state diagram I came up has 6 states and it''s named SEE1, SEE11,
SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in
the input. Because it just came from SEE1 and before SEE1, it came
from SEE000, so at SEE1 it can not change ouput to 1 which is what I
have specified that state''s ouput to be.
Anyone knows how to solve this problem? Or maybe there''s other better
ways to design the state diagram?
Thanks,
Anson
On Apr 29, 11:45 am, Peter Alfke <a...@sbcglobal.netwrote:My suggestion:
Feed the input into a 3-bit shift register.
Detect all-ones (111) and used that signal to set a latch,
detect all-zeros (000) and use that signal to reset a latch.
The latch is your de-bounced signal.
Peter Alfke
On Apr 29, 11:32 am, Anson.Stugg...@gmail.com wrote:
I''m designing adebouncefilter using Finite State Machine. TheFSM
behavior is it follows the inital input bit and thinks that''s real
output until it receives 3 consecutive same bits and it changes output
to that 3 consecutive bit until next 3 consecutive bits are received.
A reset will set theFSMto output 1s until it receives the correct
input and ouput.
This is the test sequence with input and correct output.
1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input)
1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output)
The state diagram I came up has 6 states and it''s named SEE1, SEE11,
SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in
the input. Because it just came from SEE1 and before SEE1, it came
from SEE000, so at SEE1 it can not change ouput to 1 which is what I
have specified that state''s ouput to be.
Anyone knows how to solve this problem? Or maybe there''s other better
ways to design the state diagram?
Thanks,
Anson- Hide quoted text -
- Show quoted text -Thanks Peter for the suggestion. But my problem is coming up with the
state diagram for this FSM. How can I implement what you suggested on
a state diagram? Thanks.
Anson
An************@gmail.com wrote:I''m designing a debounce filter using Finite State Machine. The FSM
behavior is it follows the inital input bit and thinks that''s real
output until it receives 3 consecutive same bits and it changes output
to that 3 consecutive bit until next 3 consecutive bits are received.
A reset will set the FSM to output 1s until it receives the correct
input and ouput.
This is the test sequence with input and correct output.
1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input)
1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output)
The state diagram I came up has 6 states and it''s named SEE1, SEE11,
SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in
the input. Because it just came from SEE1 and before SEE1, it came
from SEE000, so at SEE1 it can not change ouput to 1 which is what I
have specified that state''s ouput to be.
Anyone knows how to solve this problem? Or maybe there''s other better
ways to design the state diagram?I''m not sure I understand your terminology, but I am
assuming that that state neames mean:
SEE1 = output = 0 after 1 has been input 1 times in a row.
SEE11 = output = 0 after 1 has been input 2 times in a row.
SEE111 = output = 1 after 1 has been input 3 times in a row
(or a 1 is input after 0 has been input less than 3
times in a row).
SEE0 = output = 1 after 0 has been input 1 times in a row.
SEE00 = output = 1 after 0 has been input 2 times in a row.
SEE000 = output = 0 after 0 has been input 3 times in a row
(or a 0 is input after 1 has been input less than 3
times in a row).
If this is the case, then the 12 transitions are:
before input after
SEE1 1 SEE11
SEE1 0 SEE000
SEE11 1 SEE111
SEE11 0 SEE000
SEE111 1 SEE111
SEE111 0 SEE0
SEE0 1 SEE111
SEE0 0 SEE00
SEE00 1 SEE111
SEE00 0 SEE000
SEE000 1 SEE1
SEE000 0 SEE000
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