如何在Makefile中包含干净目标? [英] How to include clean target in Makefile?

问题描述

我有一个看起来像这样的Makefile

I have a Makefile that looks like this

CXX = g++ -O2 -Wall

all: code1 code2

code1: code1.cc utilities.cc
   $(CXX) $^ -o $@

code2: code2.cc utilities.cc
   $(CXX) $^ -o $@

我接下来要做的是包含clean target，以便每次 我运行make，它将在创建新的二进制文件之前自动删除code1和code2的现有二进制文件.

What I want to do next is to include clean target so that every time I run make it will automatically delete the existing binary files of code1 and code2 before creating the new ones.

我试图将这些行放在makefile的末尾，但这是行不通的

I tried to put these lines at the very end of the makefile, but it doesn't work

clean: 
    rm -f $@
    echo Clean done

什么是正确的方法?

推荐答案

在makefile语言中，$@表示目标名称"，因此rm -f $@转换为rm -f clean.

In makefile language $@ means "name of the target", so rm -f $@ translates to rm -f clean.

您需要向rm指定要删除的内容，例如rm -f *.o code1 code2

You need to specify to rm what exactly you want to delete, like rm -f *.o code1 code2

这篇关于如何在Makefile中包含干净目标?的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！