Makefile通用目标规则 [英] Makefile generic target rule

问题描述

我正在尝试改进我的makefile的幼稚解决方案(用于编译目标的单个规则以及用于将所有先前目标链接在一起的附加规则). 我想出了以下Makefile(已裁剪):

I'm trying to improve the naive solution (single rules for compiling targets and additional one for linking all the previous targets together) which I used im my makefile. I came up with the following Makefile (clipped):

.PHONY: clean

BASE_DIR = ../

CC = gcc
CROSS_COMPILE = arm-none-eabi-
CFLAGS =-g -I${BASE_DIR}/include 
LDFLAGS =-L${BASE_DIR}/lib -Ttarget.ld -nostdlib 

SOURCES = first.c second.c third.c fourth.c
OBJECTS = $(SOURCES:.c=.o)
EXECUTABLE = $(OBJECTS:.o=)

all: $(EXECUTABLE)

%:
    ${CROSS_COMPILE}$(CC) $(CFLAGS) $(LDFLAGS) $*.c -o $*

clean:
    rm ${EXECUTABLE}

这工作正常，但我想将编译和链接过程分开.因此，我尝试对其进行如下修改:

This works fine but I'd like to separate the compilation and linking processes. Therefore I tried to modify it as follows:

.PHONY: clean

BASE_DIR = ../

CC = gcc
CROSS_COMPILE = arm-none-eabi-

CFLAGS =-c -g -I${BASE_DIR}/include 
LDFLAGS =-L${BASE_DIR}/lib -Ttarget.ld -nostdlib 

SOURCES = first.c second.c third.c fourth.c
OBJECTS = $(SOURCES:.c=.o)
EXECUTABLE = $(OBJECTS:.o=)

all : $(EXECUTABLE)

%.o : %.c
    @echo "Compiling c file into o file"
    ${CROSS_COMPILE}$(CC) $(CFLAGS) $< -o $@

% : %.o
    @echo "Linking o file into executable"
    ${CROSS_COMPILE}$(CC) $(LDFLAGS) $< -o $@

clean:
    rm ${EXECUTABLE}

这可以正常工作，然后我以例如make first.o; make first，或者如果我将EXECUTABLE = $(OBJECTS:.o=)修改为EXECUTABLE = $(OBJECTS:.o=.out)，并且将% : %.o修改为%.out : %.o.但是，如果我尝试以make或make first的方式调用编译，则使用隐式规则.

This works ok then I invoke the Makefile as e.g. make first.o; make first or if I modify the EXECUTABLE = $(OBJECTS:.o=) to EXECUTABLE = $(OBJECTS:.o=.out) and % : %.o to %.out : %.o. If, however, I try to invoke compilation as make or make first the implicit rules are used.

我尝试过Makefile手册，但是里面确实有很多信息，我有些困惑.

I tried going through the Makefile manual but there is really a lot of information in there, I got a little confused.

如何修改Makefile，使其可以同时调用分别作为make <target>和所有目标作为make的构建目标?

How can I modify the Makefile to be allowed to invoke building separate targets as make <target> or all the targets as make as the same time?

推荐答案

描述问题所在的段落非常混乱且难以理解.提出问题时，请确保描述问题的部分最清楚:如果提供示例输出来确切显示您键入的命令和获得的结果，并解释您期望获得的结果，这将很有帮助.

The paragraph where you describe your problem is very confusing and hard to understand. When asking questions please be sure that the section describing the problem is the most clear: it's helpful if you provide sample output showing exactly what commands you typed and the results you got, and explain what you expected to get instead.

但是，我的解释是，如果您运行make first，它将使用内置规则直接从first.c编译first，而不是您的模式规则(请注意，内置规则和模式规则被认为是内隐规则".

However, my interpretation is that if you run make first it uses the built-in rule to compile first directly from first.c, rather than your pattern rules (note that both the built-in rules and your pattern rules are considered "implicit rules").

这是因为make将选择较短"的隐式规则链，因此首选使用一步直接从源代码构建可执行文件的规则，而不是先分两步构建对象的可执行文件.如果您不想使用内置的隐式规则，则需要使用-r标志调用make，或者使用

That's because make will choose the "shorter" implicit rule chain so the rule building an executable directly from source, in one step, rather than building the object then the executable in two steps, will be preferred. If you don't want to use the built-in implicit rule then you need to either invoke make with the -r flag, or else delete it by adding:

% : %.c

(就是这样)到您的makefile.

(just that) to your makefile.

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