在makefile中定义函数 [英] function define in makefile

问题描述

我有测试项目文件夹结构视图:

I have test project folder structure view:

TOPDIR
├── a
│   └── a.c
├── b
│   └── b.c
├── c
│   └── c.c
└── makefile

我写了一个测试文件:

CC        := gcc
LD        := ld

MAKE_DIR = $(PWD)
MODULES := a b c
SRC_DIR := $(addprefix ${MAKE_DIR}/,$(MODULES))

SRC := $(foreach sdir,$(SRC_DIR),$(wildcard $(sdir)/*.c))
OBJ := $(patsubst %.c,%.o,$(SRC))

INCLUDES := $(addprefix -I,$(SRC_DIR))

vpath %.c $(SRC_DIR)

define make-goal
$1/%.o: %.c
    $(CC) $(INCLUDES) -c $$< -o $$@
endef

all:
    $(foreach sdir,$(SRC_DIR),$(eval $(call make-goal,$(sdir))))

在制作过程中，它只是停止并显示:

during the make, it just STOPPED and shows:

makefile:37: *** prerequisites cannot be defined in command scripts.  Stop.

第37行是:

$(foreach sdir,$(SRC_DIR),$(eval $(call make-goal,$(sdir))))

我的makefile有什么问题?

what is wrong with my makefile?

推荐答案

您正在在命令内扩展make-goal .只需将其移到外面即可:

You are expanding make-goal inside a command. Just move it outside:

all: $(OBJ)

$(foreach sdir,$(SRC_DIR),$(eval $(call make-goal,$(sdir))))

请注意，在这种情况下，定义食谱然后再使用foreach-eval-call是过大的.模式规则将执行以下操作:

Note that defining a recipe, then using foreach-eval-call is overkill in this case. A pattern rule will do:

all: $(OBJ)

%.o: %.c
    $(CC) $(INCLUDES) -c $< -o $@

使用Make的隐式规则编译C文件，您甚至可以不用模式规则就可以逃脱:

You can even get away without a pattern rule, using Make's implicit rule for compiling C files:

CFLAGS += $(INCLUDES)

all: $(OBJ)

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