了解直接映射的缓存 [英] Understanding Direct Mapped Cache
问题描述
我试图理解直接映射的缓存，但这是一个非常复杂的概念.我已经写了我认为到目前为止可以理解的内容，但是不确定我是否正确.有人可以验证下面的解释是否正确吗?
例如，对于一台组装好的计算机，仅出于这个问题，RAM中有1024个存储单元(单元).这等于2 ^ 10，因此这些存储单元中每个存储单元的地址必须为10位长.
要求CPU从RAM存储器地址1100100111中获取数据.但是，CPU不会直接从RAM中的该内存地址访问数据. RAM将这些数据存储到缓存中，然后CPU从缓存中获取数据.
执行此操作的方法有多种，一种是直接映射缓存.高速缓冲存储器和ram存储器分为多个块，其中每个存储器中的块中的单元数必须相同. RAM和缓存中的块数也必须为2的幂.
在此示例中，RAM中有2 ^ 6 = 64个块，因此每个块中有1024/64 = 16个单元.可以说缓存中有2 ^ 2 = 4个块，因此缓存中有64个单元.这些数字的指数中的"6"和"2"在以后很重要.
由于RAM和高速缓存中的块数为2的幂，因此使计算变得容易.在我们的地址1100100111中，后6位标记偏移量100111(这6位来自2 ^ 6 = 64)，其余4位1100标记数据存储在其中的RAM块号.在此块编号内，还有两个其他重要编号.首先是缓存块号；这是该RAM块将存储到的缓存块.这是偏移量后的前2位，因此它将为00(2来自缓存中有2 ^ 2 = 4个块的事实).地址中其余的2个数字标记了标签.这将是11.
因此，当要求CPU从内存地址1100100111获取数据时，它将在高速缓存块编号00中查找该数据.它将把地址11的标记与保存在缓存中的标记进行比较，该缓存是一个单独的内存，用于存储有关数据来自RAM的位置的信息.如果标签相同，则命中，这是CPU寻找的数据.如果地址的标签和内存中的标签不同，则可能是未命中，并且数据不会存储在缓存中.
在这种情况下，缓存控制器将从RAM中的块编号1100中获取数据，并将其存储在缓存块编号00中，并将该块中的标记更新为11.现在，CPU可以在该块中获取数据了.
这都是正确的吗?在开始尝试理解关联和设置关联记忆之前，我需要了解这一点.
谢谢！
您的想法正确，但是您的电话号码出现错误.在您的示例中，您有一个直接映射的缓存，每个缓存4个块/行，每个16字节/单元.地址1100100111将被如下划分.使用最低有效的四位0111作为偏移量，因为它指向所需特定块的哪个单元.我认为您不小心将程序段号作为偏移量的一部分.无论如何，接下来的最低有效两位10将是块号，而最高有效四位1100将是标签.
您的理解似乎还不错.还有一点需要说明缓存块是否有效.祝你好运！
I'm trying to understand direct mapped cache, but it is a very complex concept. I have written what I think I understand so far, but I am unsure whether I am correct or not. Can somebody please verify if the explanation below is correct?
E.g, for a made up computer, just for the sake of this question, there 1024 memory locations (cells) in the RAM. This equals 2^10 so the address for each of these memory locations must be 10 bits long.
The CPU is asked to get data from the RAM memory address 1100100111. However the CPU doesn't access the data directly from this memory address in the RAM. The RAM stores this data to cache memory and then the CPU gets the data from the cache memory.
There are different ways of doing this, one being direct mapped cache. The cache memory and ram memory are divided up into blocks, where the number of cells in the blocks in each memory must be the same. The number of blocks in the RAM and cache must also be a power of 2.
In this example lets say there are 2^6 = 64 blocks in the RAM, so there are 1024/64 = 16 cells in each block. Lets say there are 2^2 = 4 blocks in the cache, so the cache has 64 cells. The "6" and "2" in the exponents of these numbers are important later on.
Because the The number of blocks in the RAM and cache is a power of 2, it makes the calculations easy. In our address 1100100111 the last 6 bits mark the offset 100111 (the 6 comes from the fact that 2^6 = 64), and the remaining 4 bits 1100 mark the RAM block number the data is stored in. Within this block number are two other important numbers. First the cache block number; this is the cache block that that RAM block would store to. This is the first 2 bits after the offset, so it will be 00 (The 2 comes from the fact that There are 2^2 = 4 blocks in the cache). The remaining 2 numbers in the address mark the tag. This will be 11.
So when the CPU is asked to get data from memory address 1100100111 it will look for this data in cache block number 00. It will compare the tag of the address 11 to the tag saved in the cache, which is a separate piece of memory used to store information about where from the RAM the data has come from. If the tags are the same this is a hit and this is the data the CPU is looking for. If the tag of the address and the tag in the memory are different, then this is a miss, and the data isn't stored in the cache.
If this is the case, the cache controller will get the data from block number 1100 in the RAM and store it in the cache block number 00, and update the tag in this block to 11. The CPU can now get the data in this block.
Is this all correct? I need to understand this before I can start to try and understand associative and set associative memory.
Thanks!
You have the right idea, but your numbers went wrong somewhere. In your example you have a direct-mapped cache of 4 blocks/lines of 16 bytes/cells each. The address 1100100111 will be divided up as follows. You use the least significant four bits 0111 as the offset because it refers to which cell of a particular block you want. I think you accidentally included the block number as part of the offset. Anyway, the next least significant two bits 10 will be the block number and the most significant four bits 1100 will be the tag.
Your understanding seems to be fine. One thing more that is necessary is a bit to indicate if the cache block is valid or not. Good luck with the associative stuff!
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