处理器如何读取内存? [英] How processor read memory?
问题描述
我正在尝试学习如何通过计算机来安排和处理内存，但是我并没有理解对齐的概念.
例如，在32位体系结构中，为什么我们说短(2个字节)如果它们完全位于单个32位字中，即使它们不位于偶数地址，也不对齐? >
因为如果处理器读取32位乘32位并且在地址x0处有一个char，则后面跟一个短字符(地址x01和x02)，然后是另一个char(x03).突然没有问题了，因为处理器读取了4个字节，所以没有剪切数据.
所以short是对齐的，不是吗?
该问题提出了一个处理器，该处理器具有32条连接至总线的导线以进行数据传输，可能还包含其他控制线.当它要从内存中获取数据时，它会在总线上放置一个地址，请求从内存中读取数据，等待数据，然后通过这32条线进行读取.
在典型的处理器设计中，这32条线连接到某个临时内部寄存器，而该寄存器本身具有与其他寄存器的连接.将这32位作为一个块移动很容易，每个位都在自己的线路上.
如果要在32位中移动某些位，则需要对其进行移位.这可以通过各种硬件来完成，例如我们将比特放入其中的移位单元，请求一定的移位量并从中读取结果.在内部，该变速箱将具有各种连接和开关来完成其工作.
通常，这样的移位单元将能够将八个位从四个位置(从位0、8、16或24开始)中的任意一个移动到基本位置(0).这样，可以通过从内存中读取32位(因为它只出现在32位块中)来实现诸如加载字节"之类的指令，然后使用移位单元来获得所需的字节.该移位单元可能没有将任意一组位(例如，从7、13或22开始)移动到基本位置所需的电线和开关.那将需要更多的电线和开关.
处理器还需要能够执行16位加载指令.为此，移位单元将能够将16位从位置0或16移动到位置0.当然，工程师可以将其设计为也将16位从位置8移动到位置0.但这需要更多的电线和开关，这会增加成本金钱，硅和能源.在许多处理器中，他们决定不花这笔钱，因此无法实现此功能.
因此，硬件在加载过程中根本无法将数据从字节1和2转移到字节0和1. (处理器中可能还有其他移位器，例如在用于实现移位指令的通用逻辑单元中，但是这些移位器通常是分开的，并且可以通过指令分派和控制机制进行访问.它们不在用于从中加载的组件中内存.)
I am trying to learn how memory is arranged and handled by a computer, and I don't catch the alignment concept.
For instance, in a 32-bit architecture, why do we say that short (2 bytes) are unaligned if they fit entirely within a single 32-bit word, even if they are not located at an even address?
Because if the processor reads 32 bits by 32 bits and a char is at address x0 then is followed by a short (address x01 and x02) then is followed by another char (x03). Suddenly there is no problem since there will be no cut data since the processor reads 4 bytes.
So the short is aligned, isn't it?
The question suggests a processor that has 32 wires connected to a bus, for data, with possibly other wires for control. When it wants data from memory, it puts an address on the bus, requests a read from memory, waits for the data, and reads it through those 32 wires.
In typical processor designs, those 32 wires are connected to some temporary internal register which itself has connections to other registers. It is easy to move those 32 bits around as a block, with each bit going on its own wire.
If we want to move some of the bits within the 32, we need to shift them. This might be done with various hardware, such as a shifting unit that we put bits into, request a certain amount of shift, and read a result from. Internally, that shifting unit will have a variety of connections and switches to do its job.
Typically, such a shifting unit will be able to move eight bits from any of four positions (starting at bits 0, 8, 16, or 24) to the base position (0). That way, an instruction such as "load byte" can be effected by reading 32 bits from memory (because it only comes in 32-bit chunks), then using the shifting unit to get the desired byte. That shifting unit might not have the wires and switches needed to move any arbitrary set of bits (say, starting at 7, 13, or 22) to the base position. That would take many more wires and switches.
The processor also needs to be able to effect a load-16-bits instruction. For that, the shifting unit will be able to move 16 bits from positions 0 or 16 to position 0. Certainly the engineers could design it to also move 16 bits from position 8 to position 0. But that requires more wires and switches, which cost money, silicon, and energy. In many processors, a decision was made that this expense was not worthwhile, so the capability is not implemented.
In consequence, the hardware simply cannot shift data from bytes 1 and 2 to bytes 0 and 1 in the course of the loading process. (There might be other shifters in the processor, such as in a general-purpose logic unit for implementing shift instructions, but those are generally separate and accessed through instruction dispatching and control mechanisms. They are not in the line of components used in loading from memory.)
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