Verilog模块警告 [英] Verilog Module Warning
问题描述
Im写入一个4位的多路复用器作为输入,并输出1个多路复用器.我有几种方法,可以使用案例,如果等等,但是却不断出现此错误:
Im writing a multiplexor of 4 bits as input and 1 as output. I have tray several ways, using cases, if, etc. but I keep getting this error:
WARNING:PhysDesignRules:367 - The signal <A<2>_IBUF> is incomplete. The signal
does not drive any load pins in the design.
WARNING:Par:288 - The signal A<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
当我在电路设计卡(Basys)中进行编程时,一切正常,但是分配给A [2]的开关不起作用,这是我的模块:
And when I program in my circuit design card (Basys), everything works fine, but the switch that is assign to A[2], doesnt work, here are my modules:
module Multi_4_1(
input [3:0] A,
input [1:0] S,
output Z
);
wire w1, w2;
Multi_2_1 a(.A(A[0]), .B(A[1]), .SEL(S[0]), .F(w1));
Multi_2_1 b(.A(A[2]), .B(A[3]), .SEL(S[1]), .F(w2));
Multi_2_1 c(.A(w1), .B(w2), .SEL(S[1]), .F(Z));
endmodule
module Multi_2_1(
input A,
input B,
input SEL,
output F
);
assign F = (~SEL&A)|(SEL&B);
endmodule
这是我将端子分配给卡的地方,但这是我在其他项目中尝试过的,并且工作正常
And this is where I assign the terminals to the card, but this I have tried it with another projects and it works fine
NET "A[3]" LOC ="B4"; # sw3
NET "A[2]" LOC ="K3";
NET "A[1]" LOC ="L3"; # sw1
NET "A[0]" LOC ="P11"; # sw0, el de la derecha
NET "S[0]" LOC ="G3"; # sw4
NET "S[1]" LOC ="F3"; # sw5
NET "Z" LOC ="M5"; # L0, el de la derecha
推荐答案
您的多路复用器设计不正确.
Your multiplexer has an incorrect design.
这是您的真值表:
S=00 => Z=A[0]
S=01 => Z=A[1]
S=10 => Z=A[3]
S=11 => Z=A[3]
因此,A [2]永远不会是输出,因此它已被卸载",并且您的综合工具正在警告您.您可能打算让Mux b使用sel(S[0])
.
Thus A[2] can never be an output, so it is 'unloaded', and your synthesis tool is warning you of this. You probably intend for Mux b to use sel(S[0])
.
这篇关于Verilog模块警告的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!