verilog模块中的reg和wire有什么区别 [英] What is the difference between reg and wire in a verilog module

问题描述

reg 和 wire 有什么区别?我们什么时候应该使用 reg，什么时候应该在 verilog 模块中使用 wire.我也注意到有时输出再次声明为 reg.例如，D 触发器中的 reg Q.我在某处读过这个 - 过程赋值语句的目标输出必须是 reg 数据类型."什么是程序赋值语句?我已经彻底搜索了这个，但无法找到明确的解释.

What is the difference between a reg and a wire? When are we supposed to use reg and when are we supposed to use wire in a verilog module. I have also noticed sometimes that a output is declared again as a reg. E.g reg Q in a D flip flop. I have read this somewhere - "The target output of procedural assignment statements must be of reg data type." What are procedural assignment statements? I have throughly googled this but was not able to find a clear explanation.

推荐答案

Wire:-

电线用于连接不同的元素.他们可以治疗作为物理线.它们可以被读取或分配.没有值被存储在他们之中.它们需要由任一连续赋值语句驱动或来自模块的端口.

Wires are used for connecting different elements. They can be treated as physical wires. They can be read or assigned. No values get stored in them. They need to be driven by either continuous assign statement or from a port of a module.

注册:-

与其名称相反，regs 不一定对应物理寄存器.它们代表数据存储元素Verilog/SystemVerilog.他们保留他们的价值，直到下一个价值是分配给他们(不是通过assign语句).他们可以合成到FF、锁存器或组合电路.(他们可能不是可合成！！！)

Contrary to their name, regs don't necessarily correspond to physical registers. They represent data storage elements in Verilog/SystemVerilog. They retain their value till next value is assigned to them (not through assign statement). They can be synthesized to FF, latch or combinatorial circuit. (They might not be synthesizable !!!)

Wires 和 Regs 来自 Verilog 时间范围.添加了 SystemVerilog一种称为逻辑的新数据类型.所以下一个问题是什么是这种逻辑数据类型以及它与我们的旧数据类型有何不同电线/注册.

Wires and Regs are present from Verilog timeframe. SystemVerilog added a new data type called logic to them. So the next question is what is this logic data type and how it is different from our good old wire/reg.

逻辑:-

正如我们所见，reg 数据类型在 Verilog 中有点误导.SystemVerilog的逻辑数据类型加法就是去掉上面的困惑.背后的想法是拥有一种称为逻辑的新数据类型至少不会给人一种硬件可合成的印象.逻辑数据类型不允许多个驱动程序.它有一个最后在多次赋值的情况下，赋值会赢得行为(这意味着它没有硬件等效性).如果多个，Reg/Wire 数据类型给出 X司机试图用不同的价值观来驱动他们.简单的逻辑数据类型分配最后一个分配值.reg/wire 的下一个区别和逻辑是逻辑可以由分配块驱动，输出一个端口和一个像这样的程序块

As we have seen, reg data type is bit mis-leading in Verilog. SystemVerilog's logic data type addition is to remove the above confusion. The idea behind is having a new data type called logic which at least doesn't give an impression that it is hardware synthesizable. Logic data type doesn't permit multiple drivers. It has a last assignment wins behavior in case of multiple assignments (which implies it has no hardware equivalence). Reg/Wire data types give X if multiple drivers try to drive them with different values. Logic data type simply assigns the last assignment value. The next difference between reg/wire and logic is that logic can be both driven by assign block, output of a port and inside a procedural block like this

  logic a;
    assign a = b ^ c;                   // wire style 
    always (c or d) a = c + d;          // reg style
    MyModule module(.out(a), .in(xyz)); // wire style

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