Verilog Reg/Wire混乱 [英] Verilog Reg/Wire Confusion

问题描述

我正在用Verilog制作一个Multicycle CPU，它由一个数据路径和一个控件组成.控件(状态机)的输出是寄存器，但数据路径之间的连接是导线.如果假设有线信号是(以伪代码形式): wire = OR(有线来自多路复用器，则控制输出为reg)，我该怎么做?您可以在Verilog中使用带有reg的电线吗?如果没有，有没有更好的方法来实现呢?控制信号输出可以在控制模块中注册，但在顶部模块中布线吗?

I'm making a Multicycle CPU in Verilog that consists of a Datapath and a Control. The outputs of the control (state machine) are registers, but the connections between the datapath are wires. If a wire signal is supposed to be (in psuedo-code): wire = OR(wire coming from a mux, reg output from control), how do I do this? Can you OR a wire with a reg in Verilog? If not is there a better way to implement this? Can the control signal outputs be registers in the control module, but wires in the top module?

使用图片进行更新以进行澄清:

Update with picture for clarification:

推荐答案

是的，您可以在Verilog中或者电线和reg输出.

Yes, you can or a wire and a reg output in Verilog.

是的，每个子模块的输出(基本上是电线)可以直接或间接内部连接到子模块中的reg.

Yes, each sub-module's outputs, which are essentially wires, can be directly or indirectly internally connected to a reg within the sub-module.

我认为这是一个很好的方法.

I think that is a fine way to do it.

现在，您甚至可以将模块的输出声明为"reg"，但这仅是语义上的糖，而不是分别声明输出和reg.我更喜欢显式方式(即q1_o和q1_reg).

Now, you can even declare the outputs of a module to be "reg", but that is just semantic sugar over declaring the output and reg separately. I like the explicit way better (i.e. q1_o and q1_reg).

module Submod(input clk_i, intput d_i, output q1_o, output reg q2_o);
    reg q1_reg;
    always @(posedge clk_i) begin
        q1_reg <= d_i;
        q2_o <= ~d_i;
    end
    assign q1_o = q1_reg;
endmodule

module Main(input clk_i, input [3:0]ext_i, output [1:0]ext_o)
    wire mux, x1, x2;

    Submod Submod_inst(clk_i, ext_i[0], x1, x2);

    assign ext_o[0] = x1;
    assign mux = ext_i[1] ? ext_i[2] : ext_i[3];

    assign ext_o[1] = mux | x2; /* something like this */
endmodule

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