wire 和 reg 的区别 [英] Difference between wire and reg

问题描述

我是 Verilog 的新手，我有不明白的问题:

I'm new in Verilog and i have question that i don't understand:

module my_func(t0, t1, t2, t3, s0, s1, res)
begin
  in t0, t1, t2, t3, s0, s1;
  out res;

  always begin
    if ( s0=0 && s1=0 )   res = t0;
    if ( s0=1 && s1=0 )   res = t1;
    if ( s0=0 && s1=1 )  res = t2;
    if ( s0=1 && s1=1 )   res = t3;
  end
endmodule

module my_FSM( input, output )
begin
  in input;
  out output;
  ¬¬__(1)__ d[3];
  __(2)__ q[3];

always @ (in)
begin
  d[0] = input | q[2];
  d[1] = input & q[0];
  my_func(0, q[0], q[1], q[2], q[1], input, d[2]);
  out = q[2] & d[1];
end

always @(posedge clk)
begin
  q = d;
end

endmodule

问题是:

填补缺失:
(1): 电线, (2): reg (这是真实的答案)

FILL The missing:
(1): wire, (2): reg (this is the truth answer )

有人可以解释为什么这是真正的答案以及wire和reg有什么不同吗?

Can someone explain why this the true answer and what the different between wire and reg?

推荐答案

从技术上讲，在 Verilog 中不需要连线声明，除非您覆盖了 `default nettype，但我想这不是我们想要的.但请记住，在 always 块中分配的内容必须是reg"类型.

wire declarations technically aren't required in Verilog, unless you have overridden `default nettype, but I imagine that's not what is desired. But remember that things assigned in an always block must be of type 'reg'.

祝你好运.

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