在 Verilog 中使用带有输入或输出的 wire 或 reg [英] Using wire or reg with input or output in Verilog

问题描述

当您将某些内容声明为输入或输出时，您如何知道是否还必须将其声明为 reg 或 wire?

When you declare something as input or output, how do you know if you have to also declare it as a reg or a wire?

推荐答案

reg 和 wire 指定对象的分配方式，因此仅对输出有意义.

reg and wire specify how the object will be assigned and are therefore only meaningful for outputs.

如果您计划以顺序代码分配输出，例如在 always 块中，请将其声明为 reg(这对于变量"来说确实是用词不当在 Verilog 中).否则，它应该是一个 wire，这也是默认的.

If you plan to assign your output in sequential code,such as within an always block, declare it as a reg (which really is a misnomer for "variable" in Verilog). Otherwise, it should be a wire, which is also the default.

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