在 verilog 或系统 verilog 中在 case 语句中生成块 [英] Generate block inside case statement in verilog or system verilog
问题描述
Verilog 或 SystemVerilog 有没有办法在 case 语句中插入 generate 语句来生成所有可能的输入组合.例如,一个典型的用例是 N:1 多路复用器.
Is there a way in Verilog or SystemVerilog to insert generate statement inside case statement to generate all the possible input combinations. For example a typical use case would be for a N:1 mux.
case(sel)
generate
for(i = 0; i < N; i += 1)
i: out = q[i];
endgenerate
endcase
我试过这个,但该工具出错.可以使用另一种语法,即
I tried this, but the tool gives error. An alternate syntax is available which is
out <= q[sel];
但是,我的工具不理解这一点(多路复用器已完全解码)并生成组合循环.我可以使用 if
语句来获得预期的多路复用器.但是,我想知道是否有更好的方法来做到这一点.
But, my tool is not understanding this(the mux is fully decoded) and generating combinational loops. I can use if
statement to get the expected mux. But, I was wondering if there was a better way to do it.
推荐答案
你不能像这样混合 for
和 case
.如果你只是想写一个多路复用器,看看这个老问题:How使用 SystemVerilog 定义参数化多路复用器
You can't mix a for
and a case
like that. If you're just trying to write a multiplexer, have a look at this older question: How to define a parameterized multiplexer using SystemVerilog
唯一的区别是选择信号应该是单热编码的.对于您的情况,您将拥有:
The only difference there is that the select signal is supposed to be onehot encoded. For your case you would have:
always_comb begin
out = 'z;
for (int i = 0; i < N; i++) begin
if(sel == i)
out = q[i];
end
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