在 verilog 中使用带有 for 循环的生成 [英] Using a generate with for loop in verilog

问题描述

我试图理解为什么我们在 verilog 中使用 generate 和 for 循环.

I'm trying to understand why we use generate in verilog along with a for loop.

一起使用 generate 和 for 循环:

Using a generate and for loop together:

reg [3:0] temp;
genvar i;
generate
for (i = 0; i < 3 ; i = i + 1) begin: 
    always @(posedge sysclk) begin
        temp[i] <= 1'b0;
    end
end
endgenerate

仅使用 for 循环:

Using only for loop:

reg [3:0] temp;
genvar i;
always @(posedge sysclk) begin
  for (i = 0; i < 3 ; i = i + 1) begin: 
    temp[i] <= 1'b0;
    end
end

我认为这两个片段基本上会产生相同的结果，即 temp[0] 到 temp[10] 等于值 0.在这种情况下，我们通过使用 generate 语句看到的区别/优势是什么?

I'm considering the two snippets would basically produce the same result i.e. temp[0] to temp[10] equal to value 0. What is the difference/advantage we see by using a generate statement in this case ?

推荐答案

一般来说，generate for 循环和常规 for 循环的主要区别在于 generate for 循环为每次迭代生成一个实例.这意味着在您的示例中将有 3 个始终块(而不是常规循环中的 1 个块).

In general, the main difference between generate for loop and regular for loop is that the generate for loop is generating an instance for each iteration. Meaning that in your example there will be 3 always blocks (as opposed to 1 block in the regular loop case).

需要生成的代码的一个很好的例子是:

A good example of code that requires generate for is:

module A();
..
endmodule;

module B();
parameter NUM_OF_A_MODULES = 2; // should be overriden from higher hierarchy
genvar i;
for (i=0 i<NUM_OF_A_MODULES; i=i+1) {
  A A_inst();
}
endmodule;

在此示例中，常规 for 无法完成创建 NUM_OF_A_MODULES 个实例的工作.

In this example a regular for cannot do the work of creating NUM_OF_A_MODULES instances.

在您的示例中，您可以通过两种方式获得所需的结果.(只要你修复了一些小错误:))

In your example, you can acheive the required result in both ways. (as long as you fix some minor bugs :) )

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