循环收敛 - Verilog 综合 [英] Loop Convergence - Verilog Synthesis

问题描述

我正在尝试连续减去特定数字以获得数字的最后一位(不除法).例如当 q=54 时，循环后我们得到 q=4.q=205 也是一样，输出是 q=5.

I am trying to successively subtract a particular number to get the last digit of the number (without division). For example when q=54, we get q=4 after the loop. Same goes for q=205, output is q=5.

  if(q>10)
    while(q>10)
    begin
    q=q-10;
    end

迭代应该在逻辑上收敛.但是，我收到一个错误:[Synth 8-3380] 循环条件在 2000 次迭代后不收敛"

The iteration should converge logically. However, I am getting an error: "[Synth 8-3380] loop condition does not converge after 2000 iterations"

我查看了帖子 - 在始终块中使用 For 循环.它说循环中的迭代次数必须是固定的.

I checked the post - Use of For loop in always block. It says that the number of iterations in a loop must be fixed.

然后我尝试使用固定迭代来实现这个循环，如下所示(只是为了检查这是否至少合成):

Then I tried to implement this loop with fixed iterations as well like below (just for checking if this atleast synthesizes):

if(q>10)
    while(loopco<9)
    begin
    q=q-10;
    loopco=loopco-1;
    end

但是上面的方法也行不通.得到相同的错误[Synth 8-3380] 循环条件在 2000 次迭代后不收敛".从逻辑上讲，应该是 10 次迭代，因为我已经声明了 loopco=8 的值.

But the above does not work too. Getting the same error "[Synth 8-3380] loop condition does not converge after 2000 iterations". Logically, it should be 10 iterations as I had declared the value of loopco=8.

有关如何在 verilog 中实现上述功能的任何建议都会有所帮助.

Any suggestions on how to implement the above functionality in verilog will be helpful.

推荐答案

那个代码不能合成.对于综合，循环必须具有编译时间已知的迭代次数.因此它必须知道要进行多少次减法.在这种情况下，它不能.

That code can not be synthesized. For synthesis the loop has to have a compile time known number of iterations. Thus it has to know how many subtractions to make. In this case it can't.

永远不要忘记，为了综合，您正在将语言转换为硬件.在这种情况下，该工具需要生成 N 次减法的代码，但 N 的值未知.

Never forget that for synthesis you are converting a language to hardware. In this case the tool needs to generate the code for N subtractions but the value of N is not known.

您已经声明您正在努力避免分裂.这暗示我你知道通用除法运算符不能合成.尝试使用重复减法来解决这个问题是行不通的.你应该怀疑:如果这很容易，现在早就完成了.

You are already stating that you are trying to avoid division. That suggest to me you know the generic division operator can not be synthesized. Trying to work around that using repeated subtract will not work. You should have been suspicious: If it was the easy it would have been done by now.

如果您知道 q 的上限(您可以根据位数确定)，则可以自己构建它:

You could build it yourself if you know the upper limit of q (which you do from the number of bits):

wire [5:0] q;
reg  [3:0] rem;
always @( * )
   if (q<6'd10)
      rem = q;
   else if (q<6'd20)
      rem = q - 6'd10;
   else if (q<6'd30)
      rem = q - 6'd20;
   etc.
   else
      rem = q - 6'd60;

刚刚注意到这个链接会在您的问题旁边弹出，显示过去曾有人问过这个问题:如何不使用 while() 循环在verilog中(用于综合)?

Just noticed this link which pops up next to your question which shows it has been asked in the past: How to NOT use while() loops in verilog (for synthesis)?

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