如何在Verilog综合中比较整数值与for循环中的二进制以生成延迟? [英] How to compare integer values with binary in for loop for Delay Generation in Verilog Synthesis?
问题描述
朋友您好，我仍然不知道如何在Verilog中生成延迟对于合成，并在Verilog中将其称为任何行进行合成...为找到此代码，我编写了一个代码，但它不起作用，如果您知道如何生成延迟，请帮帮我并在任何行中调用，例如C的Function * ............实际上，Friends如果您在这里告诉我为什么我要使用Loop，那么我的答案是-我要在for循环内移动指针，直到和除非他们完成了我为延迟生成所做的计算..
module state_delay;
reg Clk=1'b0;
reg [3:0]stmp=4'b0000;
integer i,a;
always
begin
#50 Clk=~Clk;
end
always @(posedge Clk)
begin
a=1'b1;
delay();
a=1'b0;
delay();
a=1'b1;
end
task delay();
begin
for(i=0;i==(stmp==4'b1111);i=i+1)
begin
@(posedge Clk)
begin
stmp=stmp+1;
end
end
if(stmp==4'b1111)
begin
stmp=4'b0000;
end
end
endtask
endmodule
实际上我想要这个朋友 a = 1'b0;延迟(); a = 1'b1; ，请帮助我以前已经尝试过使用Counter延迟生成，但不适用于我.....如果您知道使用 Counter ，请告诉我. ....谢谢
此问题是如何在Verilog使用Counter for Synthesis并在Always Block内部调用?.
我发现有一段代码很麻烦:
always @(posedge Clk) begin
a = 1'b1;
delay() ;
a = 1'b0;
end
NB:一个要坚持的好规则是在边缘触发的进程中始终使用<=.
#10ns;的任务，我们在当前代码中得到的是:time 0ns a = x;
time 1ns a = 1; //Posedge of clk
time 6ns a = 1; //Waiting on delay
time 11ns a = 0; //Delay completed
使用<=，我认为您应该会看到类似的行为.但是，当涉及到综合延迟时，无法创建像#1ns这样的延迟，整个过程将崩溃到:
always @(posedge Clk) begin
a <= 1'b0;
end
使用硬件描述语言，一个好的方法是考虑我们要隐含的硬件并用该语言描述它.构造always @(posedge Clk)用于表示触发器，即每个时钟周期输出更改一次.在这个问题中，我们有a改变值3次，从1个时钟沿开始，我不知道您要暗示什么硬件.
您不能提供内联可综合延迟.对于要合成的always @(posedge clk)块，它们应该能够在零时间内执行.您需要引入状态机，以在时钟沿之间保持状态.我想我已经在我以前的答案中提供了一个很好的示例.如果延迟是可编程的，请参见 mcleod_ideafix的答案.
Hello Friends I still not know how to Generate Delay in Verilog For synthesis and call it any line in Verilog for synthesis...for finding this I write a code but it not works please help me if you know how to Generate Delay and call in any line like a C's Function*......Actually Friends if you tell me why I use for Loop here then my answer is - I want to move pointer inside for loop until and unless they completes its calculation that I made for Delay Generation..
module state_delay;
reg Clk=1'b0;
reg [3:0]stmp=4'b0000;
integer i,a;
always
begin
#50 Clk=~Clk;
end
always @(posedge Clk)
begin
a=1'b1;
delay();
a=1'b0;
delay();
a=1'b1;
end
task delay();
begin
for(i=0;i==(stmp==4'b1111);i=i+1)
begin
@(posedge Clk)
begin
stmp=stmp+1;
end
end
if(stmp==4'b1111)
begin
stmp=4'b0000;
end
end
endtask
endmodule
Actually friends I want this a=1'b0; delay(); a=1'b1; please help I already tried delay Generation Using Counter previously but it not works for me.....If you know same using Counter then please tell me......Thanks
This question is a more succinct version of How to generate delay in verilog using Counter for Synthesis and call inside Always block?.
There is one section of code that I find troublesome:
always @(posedge Clk) begin
a = 1'b1;
delay() ;
a = 1'b0;
end
NB: A good rule to stick to is to always use <= in edge triggered processes.
for now lets think of the delay(); task as #10ns; What we get with the current code would be:
time 0ns a = x;
time 1ns a = 1; //Posedge of clk
time 6ns a = 1; //Waiting on delay
time 11ns a = 0; //Delay completed
Using <= and I think you should see a similar behaviour. However when it comes to synthesis delays like #1ns can not be created and the whole thing will collapse back down to :
always @(posedge Clk) begin
a <= 1'b0;
end
With a hardware description language a good approach is to consider what hardware we want to imply and describe it in the language. The construct always @(posedge Clk) is used to imply flip-flops, that is the output changes once per clock cycle. In the question we have a changing value 3 times, from 1 clock edge I do not know what hardware you are trying to imply.
You can not provide an inline synthesizable delay. For always @(posedge clk) blocks to be synthesizable they should be able to execute in zero time. You need to introduce a state machine to keep state between clock edges. I think I have already provided a good example on how to do this in my previous answer. If the delay is to be programmable then see mcleod_ideafix's answer.
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