方式初始化，提供Verilog常数值综合二维数组 [英] Way to initialize synthesizable 2D array with constant values in Verilog

问题描述

在VHDL，我可以很容易地做到这一点：

in VHDL, I can easily do this:

constant    cmdbytes       : bytearray(0 to Total) := (x"05", x"00", x...};

我想综合常数，使得FPGA启动时，这个数组有我提供的数据。这些寄存器连接到VCC或地重新present 1或0。然后我可以使用它们来生成波形。此外，我想有二维字节数组这是在世界上的Verilog 3D。

I want synthesizable constants so that when the FPGA starts, this array has the data I supplied. These registers are wired to VCC or ground to represent 1 or 0. I can then use them to generate a waveform. Also I would like to have 2D byte array which is 3D in verilog world.

推荐答案

如果你只是使用数组来一次拉出一个值，怎么样使用情况语句？诚然，这是做的长篇大论方式，但你总是可以编写一个脚本写的RTL你。

If you're just using the array to pull out one value at a time, how about using a case statement? Granted, it's a long-winded way of doing it, but you could always write a script to write the RTL for you.

reg [7:0] value;
reg [7:0] i;

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)
        i <= 8'd0;
    else
        i <= i + 1;
end

always @(*) begin
    case(i) 
        8'h00: value = 8'd0;
        8'h01: value = 8'd34;
        ...
    endcase
endcase

另一种方法是使用初始语句。据我所知，FPGA综合工具将允许您在以下方式设置阵列初始值。同样，一个脚本写这可能是要走的路。

Another way is to use an initial statement. As far as I'm aware, FPGA synthesis tools will allow you to set initial values for arrays in the following manner. Again, a script to write this may be the way to go.

reg [0:35][7:0] my_array;

initial begin
    my_array[0] = 8'd45;
    my_array[1] = 8'd26;
    ...
end

如果你的FGPA的综合工具支持某些SystemVerilog的，你就可以初始化数组，像这样：

And if your FGPA synthesis tools support some SystemVerilog, you'll be able to initialise the array like so:

reg [0:34][7:0] my_array = '{ 8'd90, 8'd34, ... }; // note the '{

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