如何在verilog中生成一组连续的 [英] how to generate a set of continuous one in verilog

问题描述

我希望在verilog中生成一组连续的像

I hope to generate a set of continuous one in verilog like

3 -> 'b111
4 -> 'b1111
5 -> 'b11111

我希望我可以使用{num{1'b1}}，但我发现该值必须是常量.在verilog中有什么方法可以生成一组连续的值吗?

I hope I can use {num{1'b1}}, but I found that the value must be constant. Is there any way in verilog that I can generate the a set of continuous one value?

推荐答案

使用系统 verilog，您可以使用 '1 语法，该语法会根据左侧自动调整大小.

Using system verilog you can use the '1 syntax which automatically sizes correctly against the left hand side.

此外，Dodon Victors 答案中的上述函数 2^N - 1 只是符号符号中的 -1.我已经展示了下面两者的用法.

Also the above function 2^N - 1 in Dodon Victors answer is just -1 in signed notation. I have shown the usage of both below.

某些模拟器可能无法在宽度大于 32 的情况下正常工作，但我相信所有现代模拟器都已解决此问题.

Some simulators may not work correctly with widths greater than 32, although I believe all modern simulators have fixed this issue.

以下关于 EDAPlayground 的示例:

module dut;

  logic [65:0] test1;
  logic [65:0] test2;

  initial begin
    #1ps;
    test1 = '1;
    test2 = -1;

    #1ps;
    $displayb(test1);
    $displayb(test2);
  end
endmodule

输出:

# 111111111111111111111111111111111111111111111111111111111111111111
# 111111111111111111111111111111111111111111111111111111111111111111

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