Verilog:你能把“赋值"吗?always@ 或 begin/end 语句中的语句? [英] Verilog: Can you put "assign" statements within always@ or begin/end statements?

问题描述

这允许吗?

input w;
     input [8:0]y;
     output reg [8:0]x;
     always@(w)
     begin


     //x[0] or A is never on in any next state
     assign x[0] = 0;
     assign x[1]= (y[0]&~w) | (y[5]&~w) | (y[6]&~w) | (y[7]&~w) | (y[8]&~w); //B
     assign x[2]= (y[1]&~w); //C
     assign x[3]= (y[2]&~w); //D
     assign x[4]= (y[3]&~w) | (y[4]&~w); //E
     assign x[5]= (y[0]&w) | (y[1]&w) | (y[2]&w) | (y[3]&w) | (y[4]&w); //F
     assign x[6]= (y[5]&w);
     assign x[7]= (y[6]&w);
     assign x[8]= (y[7]&w) | (y[8]&w);

     end

推荐答案

您可以，这称为程序连续分配".它覆盖了普通的程序分配，在您发布的代码中似乎没有调用它们.我不确定它们是否可合成，但无论如何我都没有理由使用它们.

You can, it's called a "Procedural Continuous Assignment". It overrides ordinary procedural assignments, there doesn't seem to be a call for them in the code you've posted. I'm not sure if they're synthesisable, but I never have cause to use them anyway.

代码注释 - 您的敏感度列表中缺少 y:例如 always @( w or y ) 或 always @(*) 更安全.

A note on your code - you're missing y from your sensitivity list: eg always @( w or y ) or always @(*) is safer.

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