如何定义VHDL组件和程序包? [英] How to define a VHDL component and package?
问题描述
下面我确实有以下两个VHDL文件.带有 component x 的文件 x.vhd ，需要在文件 top.vhd 作为包装.
Below I do have following two VHDL files. The file x.vhd with a component x which needs to be referenced (included) in the file top.vhd as a package.
-- x.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package x_pkg is
component my_x
port(clk_clk : in std_logic := '0';
reset_reset_n : in std_logic := '0';
end component my_x;
end package x_pkg;
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity x is
port (
clk_clk : in std_logic := '0'; -- clk.clk
reset_reset_n : in std_logic := '0'; -- reset.reset_n
);
end entity x;
architecture rtl of x is
此软件包需要在以下顶级文件中引用:
This package needs to be referenced in following top-file:
-- top.vhd
library ieee;
use ieee.std_logic_1164.all;
library altera;
use altera.altera_syn_attributes.all;
use work.x_pkg.all;
entity EyeTracker_Top is
port
(
Nios_Clk : in std_logic;
Nios_Reset_n : in std_logic;
);
end EyeTracker_Top;
architecture struct of EyeTracker_Top is
begin
M1 : my_x port map(Nios_Clk, Nios_Reset_n); -- Here I get the error message!
编译后，出现以下错误信息:
After compiling, it get following error message:
***错误(12006):节点实例"M1"实例化了未定义的实体"my_x"
***Error (12006): Node instance "M1" instantiates undefined entity "my_x"
这是什么问题?我想套件参考有问题...
What is the problem here? I guess there is something wrong with the package reference...
谢谢！
推荐答案
您正在实例化组件my_x.组件只是一个声明，是一种空壳.每个组件实例化都必须在某个时候绑定到实际的实体/架构对.此绑定必须使用显式配置来完成.有几种方法可以做到这一点.一种是添加:
You are instantiating a component my_x. A component is just a declaration, a kind of empty shell. Every component instantiation must at some point be bound to an actual entity/architecture pair. This binding must be done with an explicit configuration. There are several ways to do this. One is to add:
for all: my_x use work.x(rtl);
在体系结构的声明区域中的
(在architecture和begin之间).当然，在详细说明顶层之前，必须在用作work的库中编译实体x及其体系结构rtl.
in the declaration area of your architecture (between architecture and begin). Of course, the entity x and its architecture rtl must be compiled in the library you use as work before you can elaborate your top level.
您得到的错误消息很难理解，因为您的工具尝试基于名称应用默认配置策略:对于未绑定的组件实例，它将搜索与该组件同名的实体.由于找不到任何内容，因此它抱怨缺少实体，这是组件绑定问题，即缺少配置.更好的工具会告诉您组件my_x的M1实例未绑定.
The error message you got is difficult to understand because your tool tries to apply a default configuration strategy based on names: for unbound instances of components it searches an entity with the same name as the component. Because it found none, it complains about a missing entity while it is a component binding problem, that is, a missing configuration. A better tool would tell you that the M1 instance of component my_x is not bound.
最后一点:如果所有这些组成部分对于您的需求来说太复杂了，请摆脱它并直接实例化您的实体:
A last note: if all this component stuff is too complicated for your needs, just get rid of it and directly instantiate your entity:
M1: entity work.x(rtl) port map(Nios_Clk, Nios_Reset_n);
，您将不需要任何组件声明和配置.
and you will need no component declaration and no configuration.
基本上有两种方法:
- 具有组件实例化和配置的自上而下的设计，
- 自下而上的设计，带有实体实例化，没有组件，也没有配置.
要了解两者之间的区别，它们的优缺点并不容易.在那里，一本好的VHDL书可能比stackoverflow上的问题和答案要好.
Understanding the differences between the two, their pros and cons is not easy. And there, a good VHDL book is probably better than questions and answers on stackoverflow.
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