您将如何处理这种数字逻辑系统中的特殊情况? [英] How would you handle a special case in this digital logic system?
问题描述
我将此数字逻辑图发布为 answer 来另一个stackoverflow问题.它描述了一种逻辑系统，该逻辑系统将用Verilog或VHDL进行编码，并最终在FPGA中实现.
替代文本http://img145.imageshack.us/img145/5125/bitshifterlogicdiagramkn7 .jpg
图中的数字框表示字段中的位.每个字段都有 K 位，并且 current 和 mask 的位将由计算机系统(使用锁存寄存器或等效寄存器)提供. 下一个中的位将被读回到同一计算机系统中.
我发布的解决方案只要在 mask 字段中至少设置了一位，并且在 current 位字段中恰好设置了一位，就可以使用.这个想法是，在计算机系统执行了某些任务(原始问题中的调度操作)之后，下一个位字段将变为当前位字段.
所以，我的问题是这样的: 您将如何修改此系统，使其能够正确处理 current 位字段全为零(未设置任何位)的特殊情况?就目前而言，如果所有位都在当前为零，无论掩码中的位设置为什么，输出也将为零.
理想地，如果 current 全部为零，则应在 next 中设置 mask 中的最低设置位.该系统还应保持可扩展到任意数量的位(K)，而不必增加更多的逻辑门.最初的问题是要提出一种解决方案，该解决方案对于任何数量的位都可以直接实现.
另请参见:此stackoverflow问题
对我来说，我会告诉FPGA用户，输入时必须将其中一位设置为1.
但是，如果这不是您的首选解决方案，那么将所有当前电流输入最初预馈入一个大的或非门的想法有什么问题(这样，只有当所有输入均为假时，输出才为真).除了Current [1]与NOR门的输出进行或"运算，然后再输入其AND门，所有的Current线也继续到达其AND门.
这样，如果所有Currents均为false，则Current [1]在进入与"门时为true.
请记住，我了解布尔代数，但我从未在原始硬件上工作过-我猜测您需要将所有输入信号缓冲到AND门中，以确保正确的时序，但我怀疑您会知道比我好.
如果SO修复了其代码/前置块，则保留下图-最新的SO更新似乎塞满了它们(使它们成比例，而不是固定宽度，字体).无论如何，eJames的图形化图表更好.
这是我的图表，比您的图表稍差:-):
I posted this digital logic diagram as an answer to another stackoverflow question. It describes a logic system which will be coded in Verilog or VHDL and eventually implemented in an FPGA.
alt text http://img145.imageshack.us/img145/5125/bitshifterlogicdiagramkn7.jpg
The numbered boxes in the diagram represent bits in a field. Each field has K bits, and the bits for current and mask will be provided by a computer system (using a latched register or equivalent). The bits in next will be read back into that same computer system.
The solution that I posted works as long as there is at least one bit set in the mask field, and there is exactly one bit set in the current bit field. The idea is that the next bit field will become the current bit field after the computer system has performed some task (a scheduling operation, in the original question).
So, my question is this: How would you modify this system so that it properly handles the special case where the current bit field is all zero (no bits set)? As it stands, if all bits in current are zero, the output will also be zero, no matter what the bits in mask are set to.
Ideally, if current is all zeroes, the lowest set bit in mask should be set in next. The system should also still remain scalable to any number of bits (K) without having to add exponentially more logic gates. The spirit of the original question was to come up with a solution that would be straightforward to implement for any number of bits.
See also: this stackoverflow question
For me, I would tell the user of the FPGA that they must have one of the bits set to 1 on entry.
However, if that's not your preferred solution, what's wrong with the idea of pre-feeding all the Current inputs initially into a big NOR gate (so that the output is true only when all inputs are false). All Current lines also continue through to their AND gates with the exception that Current[1] is OR'ed with the output of our NOR gate before entering it's AND gate
That way, Current[1] would be true entering the AND gate, if all Currents are false.
Keep in mind that I understand boolean algebra but I've never worked on raw hardware - I'm guessing you'll need to buffer all the input signals into the AND gates to ensure correct timing but i suspect you'll know that better than I.
The following diagram is left in in case SO fixes its code/pre blocks - the latest SO update seems to have stuffed them up (leaving them proportional, not fixed-width, font). Anyway, eJames' graphical diagram is better.
Here's my diagram, slightly less elegant than yours :-):
+-------------------+
| |
| +---- |
Current[1]-----+------\ \ |
|NOR|o--+ |
Current[2-k]---+------/ / | |
| +---- | |
| +\ /+
| | \_/ |
+---+ | OR |
\ /Buffer \ /
+ ---
| |
+---+ +---+
|2-k| | 1 | <- These signals feed
+---+ +---+ into your AND gates.
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