如何处理数字逻辑模拟器中的循环? [英] How to handle loops in a digital logic simulator?

问题描述

我正在开发一个数字逻辑模拟器，以便稍后在其中构建自己的CPU(这是一个长期的项目).对于没有循环的电路，例如fulladder，一切都很好.然后是像SR锁存器这样的电路，其中一个门的输入之一连接到另一个门的输出.所以我处于循环中，因为两个门都需要另一个门的输出来计算自己的输出.
解决此问题的最佳方法是什么?我以某种方式实现了该功能(当检测到循环时)将返回其最后的输出.或者，当该运行是第一次运行时(因此没有以前的输出)，我将返回零(低).所以我只是假设所有输出在一开始都是低/零.到目前为止，它仍然有效，但是我敢肯定这不是解决问题的好方法.

I'm developing a digital logic simulator to build my own CPU in it later (so it's a long term project). Everything works great for circuits with no loops, for example a fulladder. Then there are circuits like an SR latch, where one of the inputs of a gate is connected to the output of another gate. So I'm in a loop, because both gates need the output of the other one, to compute their own output.
What is the best way to solve this? I implemented it in a way, that (when a loop is detected) it will return it's last output. Or, when this run is the first one (so there was no previous output) I will return zero (low). So I just assume that all the outputs were low/zero in the beginning. It works so far, but I'm sure that this is not a good way to solve the issue.

有什么想法吗?

推荐答案

在许多情况下，简单地将每个门建模为具有单位传播延迟是一种很好的方法.稍微复杂一点的替代方法是让大多数组件使用仿真步骤"例程检查仿真时间是否提前了整步"，如果是则仅更新其输出.可以省略一些组件的检查，而是要求在其他组件有机会更新之后在模拟步骤中再次运行它们.只要它们没有嵌套得太深，这将允许某些组件假装为零传播延迟(模拟应该限制在决定组件不打算运行每个组件的评估状态例程之前，它将尝试运行多少次.达到稳定状态).

In many cases, simply modeling each gate as having a unit propagation delay is a fine approach. A slightly more sophisticated alternative is to have the "simulation-step" routine for most component check whether the simulation time has advanced by a "full step", and only update its output if so; a few components could be omit that check but instead request that they be run again on the simulation step after other components have had a chance to update. That would allow some components to pretend to have zero propagation delay provided that they weren't nested too deeply (the simulation should limit how many times it will attempt to run each component's evaluate-state routine before it decides the components aren't going to reach a stable state).

根据精确模拟的内容，我建议除了高"和低"之外，还为组件提供多个输出状态.甚至添加不确定"状态也可能会有所帮助，因为当组件的输入以可能影响其输出的方式更改时，输出将在最小传播时间后变为不确定"，并在最大传播时间后取合法值.输入生效后的传播时间.请注意，随着信号通过更多级别的逻辑，信号不确定"的时间将增加.有意义地模拟任何事情的唯一方法是拥有一个假定稳定的时钟，并确保时钟周期足够长，以使它们之间能够完全稳定.

Depending upon what exactly is being simulated, I would suggest having multiple output states for your components besides "high" and "low". Even adding an "indeterminate" state can be helpful, with the behavior that when a component's input changes in a way that could affect its output, the output will become "indeterminate" after the minimum propagation time, and assume a legitimate value after the maximum propagation time following the moment that the inputs become valid. Note that as signals pass through more levels of logic, the amount of time that they are "indeterminate" will increase. The only way to simulate anything meaningfully is to have a clock which is assumed stable, and ensure that clock periods are long enough that things can fully stabilize between them.

以这种方式进行模拟的优点是，尽管模拟将在许多实际可行的电路上失败"(产生不确定的"值)，但这种模拟产生确定的结果这一事实表明，真正的电路可以以同样的方式建造.不幸的是，对于依赖于边沿触发的锁存器的电路，最常见的仿真结果将是不确定的"，即使对于实际工作机会为100％的电路也是如此.为了缓解这一问题，人们通常希望限制"几个门，以免延长不确定"的时间间隔.这样做将是骗子"，并可能使电路可能在仿真中工作，但实际上可能会失败.尽管如此，如果仔细地进行这种作弊，它们可能会使模拟比其他方式有用得多.

Simulating things in this way has the advantage that while simulation will "fail" (yield "indeterminate" values) on many circuits which would work in reality, the fact that such a simulation yields deterministic results would suggest that a real circuit that was built the same way would do so as well. Unfortunately, for circuits which rely upon edge-triggered latches, the most common simulation result would be "indeterminate", even for circuits which would have a 100% chance of actually working. To ease that problem, one would often want to 'jinx' a few gates so as not to stretch the 'indeterminate' interval. Doing this would be something of a "cheat", and create the possibility that a circuit might work in simulation but fail in reality. Nonetheless, if such cheats are applied carefully, they may make simulation much more useful than it would be otherwise.

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