RISC-V可变长度指令如何详细工作? [英] How does RISC-V variable length of instruction work in detail?
问题描述
略读risc-v isa文档后，给我的印象是riscv支持16位(RVC)，32位(RV32I)和64位(RV64I)指令长度.
After skimming the risc-v isa doc, it gives me the impression that the riscv supports both 16bits(RVC), 32bits(RV32I), 64bits(RV64I) length of instructions.
对于RV32I:立即数的符号范围为32位
For the RV32I: immediate is signed extented to 32 bits
- 指令长度:32位
- 寄存器大小:32位
- 内存地址:32位
- 指令长度:32位
- 寄存器大小:64位
- 内存地址:64位
对于RV64i:立即数的符号范围为64位
For the RV64i: immediate is signed extented to 64 bits
似乎RV32I& RV64I使用32位指令大小，而差异与符号扩展的大小有关.
It seems both RV32I & RV64I use 32 bits instruction size and the difference relates to the size of sign extension.
我认为较大的指令大小使您可以在指令内部编码较大的立即数，这应该比较小的指令大小更好，因为它很容易耗尽空间.
I think large instruction size allows you to have large immediate number encoded inside the instruction, which should be better than smaller instruction size since it is very easy to run out of space.
对于risc-v RV64I，如果仅使用32位指令长度，64位寄存器文件和内存地址，则如何充分利用硬件资源. (例如，直接跳转到大内存地址.)
For risc-v, RV64I, if it only use 32 bits instruction length, with 64 bits register file and memory address, how it could sufficiently use the hardware resource. (ex. jump direct to a large memory address.)
通常，RV64I的名称是否应指示指令的长度为64位?
And in general, should the nameing of RV64I indicate the length of instruction is 64 bits?
推荐答案
RISC-V允许混合使用16位，32位，48位，64位指令以及更多指令！
RISC-V allows mixing 16-bit, 32-bit, 48-bit, 64-bit instructions, and beyond!
RV32I定义了一种32位计算机体系结构，其中的寄存器为32位宽.其指令全为32位宽.例如，它具有lw可以将32位字加载到寄存器中，而add可以添加两个寄存器并以第三个为目标.
RV32I defines a 32-bit computer architecture, where registers are 32-bits wide. Its instructions are all 32-bits wide. For example, it has lw to load a 32-bit word into a register, and, add to add two registers and target a third.
RV64I定义了一种64位计算机体系结构，其中寄存器为64位宽(因此为RV64)，其指令也为32位宽. RV32指令仍然有效，并且还有一些其他指令可以容纳32位和64位操作.例如，lw仍然加载32位字(尽管现在符号扩展为填充64位寄存器)，因此使用新的指令ld加载64位字. add仍会添加两个寄存器，并以第三个为目标，但是由于RV64中的寄存器是64位，因此相同的add现在正在执行64位加法而不是32位加法.如果这只是您想要的，新指令addw进行32位加法.
RV64I defines a 64-bit computer architecture, where registers are 64-bits wide (hence RV64) — its instructions are also 32-bits wide. The RV32 instructions still work, and there are some additional instructions to accommodate both 32-bit and 64-bit operations. For example, lw still loads a 32-bit word (though now sign extends to fill the 64-bit register), and so a new instruction is used ld to load a 64-bit word. add still adds two registers and targets a third, but this same add is now doing 64-bit addition instead of 32-bit addition, since the registers are 64-bits in RV64. A new instruction addw does 32-bit addition, in case that was all you wanted.
RVC是可以添加到RV32I或RV64I的扩展.当存在时，它允许16位指令，并且其设计是将16位指令以1:1的比例扩展为32位宽的指令-因此，(RV32或RV32的寄存器体系结构都没有更改或添加了RVC的RV64)，从某种意义上说，它们没有什么新功能可以在32位宽的指令集中实现.我们应该考虑它更多是一种节省空间的技术，而不是一些新功能.
RVC is an extension that can be added to either RV32I or RV64I. When present it allows for 16-bit instructions, and, its design is such that a 16-bit instruction expands 1:1 into a 32-bit wide instruction — because of this there are no changes to the register architecture (of either the RV32 or RV64 that RVC was added to), and in some sense, there's nothing new they can do that isn't already in the 32-bit wide instruction set. We should think of it more a space saving technique rather than some new capabilities.
基本体系结构(即没有RVC)允许分支到16位边界. PC和返回地址以及所有分支指令均支持任何偶数字节值，因此，将RVC添加到某些内容时，其他指令不会更改.该工件还支持48位和64位指令，尽管尚未为这些大小定义扩展.
The base architecture (that is, without RVC) allows for branches to 16 bit boundaries. The PC and return addresses and all branching instructions support any even byte value, so when RVC is added to something, the other instructions don't change. This artifact also supports 48-bit and 64-bit instructions, though there are no extensions defined for those sizes as yet.
但是，指令集保留了足够的操作码空间，从而可以区分16位，32位，48位和64位指令.以二进制11开头的指令(在该指令的最低位)是32位大小的指令(但保留一种模式:因此它们不能以11111开头).精简指令在同一位置使用00、01和10. 48位指令使用起始序列011111，而64位指令则从0111111开始.
However, the instruction set reserves enough opcode space to make it possible to differentiate between 16-bit, 32-bit, 48-bit, and 64-bit instructions. Instructions that start with binary 11 (in the lowest bit position of the instruction) are 32-bit sized instructions (but one pattern is reserved: so they cannot start with 11111). The compact instructions use 00, 01, and 10 in that same position. 48-bit instructions use starting sequence 011111, and 64-bit instructions start with 0111111.
基本体系结构还对所有内容都使用了pc相对分支，因此您可以构建一个具有4GB代码段的可执行映像(并且在加载时，它可以位于64位地址空间中的任何位置)./p>
The base architecture also uses pc-relative branching for everything, so you can build an executable image with a code section as large as 4GB (and when loaded, it could be located anywhere in the 64-bit address space).
似乎RV32I& RV64I使用32位指令大小，而差异与符号扩展的大小有关.
It seems both RV32I & RV64I use 32 bits instruction size and the difference relates to the size of sign extension.
RV32与RV64相比，寄存器从32位扩展到64位，因此，是的，当在RV64上进行符号扩展时，它扩展为64位.
RV32 vs. RV64, the registers expand from 32-bits to 64-bits, so, yes, when sign extension happens on RV64, it goes out to 64-bits.
我认为较大的指令大小使您可以在指令内部编码较大的立即数，这应该比较小的指令大小更好，因为它很容易耗尽空间.
I think large instruction size allows you to have large immediate number encoded inside the instruction, which should be better than smaller instruction size since it is very easy to run out of space.
RISC V指令集是在与MIPS(一种较早的RISC设计)进行了多年研究之后设计的.与具有可变长度指令大小的x86相比，MIPS在40多年的发展中没有留下足够的操作码空间.固定大小的指令集是代码空间和功能之间的折衷-指令大小越大，可以进行的编码越多，但代价是代码密度高.代码密度对性能有很大的影响，因此不能忽略.因此，RISC V允许使用大小可变的指令，并且，如果您愿意，可以在实现中创建256位指令！
The RISC V instruction set was designed after years of research with MIPS (an earlier RISC design). By comparison with x86, which has a variable length instruction size, MIPS did not leave enough opcode space for 40+ years of evolution. A fixed sized instruction set is a trade off between code space and capabilities — the larger the instruction size, the more can be encoded, at the expense of code density. Code density has a huge effect on performance, so cannot be ignored. So, RISC V allows for variable sized instructions, and if you like, you can create 256-bit instructions in your implementation!
对于risc-v RV64I，如果仅使用32位指令长度，64位寄存器文件和内存地址，则如何充分利用硬件资源. (例如，直接跳转到大内存地址.)
For risc-v, RV64I, if it only use 32 bits instruction length, with 64 bits register file and memory address, how it could sufficiently use the hardware resource. (ex. jump direct to a large memory address.)
可执行程序映像的代码最大可以为4GB，并且仍使用pc相对分支-它将使用我们称为far分支的内容，其中分支序列由两条指令(auipc和jal).需要明确的是，4GB是一个非常大的代码段. 64位体系结构的大多数价值在于能够处理超过4GB的数据，而不是超过4GB的代码.要达到超过4GB的代码大小，您将使用指针(例如存储在表中)，因为指针可以是64位宽.该技术已经用于DLL(即使将DLL的大小加在一起，它们通常通常不会超过4GB的代码)，因为它们通常是独立加载的(因此，相对于PC的分支将在单个内部工作)代码段，在代码段之间插入是无效的.
The code for a executable program image can be up to 4GB in size and still use pc-relative branching — it would use what we refer to as far branches, where the branch sequence is composed of two instructions (auipc and jal). To be clear, 4GB is a very large code segment. Most of the value of a 64-bit architecture is being able to work with over 4GB of data, not over 4GB of code. To reach code sizes over 4GB, you would use pointers (e.g. stored in tables), since pointers can be full 64-bits wide. This technique is already used for DLLs (even though they generally won't come close to exceeding 4GB of code when the size of each is added together) since they are usually loaded independently (and thus while pc-relative branches will work inside a single code section, it won't work to go in between code sections).
通常，RV64I的名称是否应指示指令的长度为64位?
And in general, should the nameing of RV64I indicate the length of instruction is 64 bits?
因为，无论我们采用哪种架构(例如16位，32位，64位)，在存储空间不足之前，我们都会先耗尽数据空间，这是64位的主要特征该体系结构支持64位地址空间，从而可以为数据提供大量内存.大型地址总线的这种支持还具有使用64位地址的能力，当然还可以操纵64位值.因此，RV64的重要之处在于64位寄存器以及使用64位值寻址内存的能力. (指令大小是一个正交的问题.)
Since, what ever architecture we have (e.g. 16-bit, 32-bit, 64-bit) we tend to run out of space for data before we run out of space for code, the dominant feature of a 64-bit architecture is its support for a 64-bit address space, allowing large amounts of memory for data. This support of a large address bus also comes with the ability use 64-bit addresses and of course also to manipulate 64-bit values. So, what's important about RV64 is the 64-bit registers and the ability to use 64-bit values to address memory. (The instruction size is an orthogonal issue.)
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