为什么ARM有64KB大页面? [英] Why does ARM have 64KB Large Pages?

问题描述

ARM720T用户手册中提到了大小页面.由于ARM 720T要求将64KB页表项在页表中重复16次，为什么不放置16个小页(4KB)项来模仿64KB页项，而不是首先使用大页?

The ARM720T user manual mentions small and large pages. Since the ARM 720T requires a 64KB page table entry to be duplicated 16 times in the page table, why not place 16 small page (4KB) entries to mimic a 64KB page entry instead of using a large page in the first place?

推荐答案

来自ARM720 TRM，

From the ARM720 TRM,

大页面 由64KB的内存块组成.大页面是 支持允许映射大范围的 记忆体，而只使用 TLB). 扩展了其他访问控制机制 到16KB子页面.

Large Pages consist of 64KB blocks of memory. Large Pages are supported to allow mapping of a large region of memory while using only a single entry in the TLB). Additional access control mechanisms are extended to 16KB Sub-Pages.

主要好处是64k条目将仅消耗一个TLB(MMU页面条目缓存). TLB是64个条目，因此64*4k = 256kB与64*64k = 4MB；不需要页表查找即可解决的内存量显着增加.

The main benefit is a 64k entry will only consume one TLB (MMU page entry cache). The TLB is 64 entries so 64*4k = 256kB versus 64*64k = 4MB; a significant increase in the amount of memory that doesn't require a page table lookup to address.

有很多缺点.例如，便携式OS(及其API)可能需要较小的页面.如果所有条目均为64k，则会导致碎片.这些节条目甚至更好，每个条目代表一个1MB的块，在TLB中可容纳64MB.通常，该部分对于 virtual == physical 映射会更好地工作.

There are many down sides. For instance, a portable OS (and it's API) might require the smaller pages. If all entries are 64k fragmentation can result. The section entries are even better with each representing a 1MB chunk with 64MB fitting in the TLB. Generally the section will work better for a virtual==physical mapping.

如果您知道系统只有4MB的可用内存，则64k页条目可以带来更可靠的性能.即使具有更大的内存大小，中断代码和数据也可以使用64k条目并带有TLB锁定 ^note 来避免页表遍历.这可以导致更好的IRQ延迟. TLB是有限的资源，因此为中断处理程序使用4k条目可能会导致浪费TLB.使用段条目可能会浪费内存，因为大多数中断代码均小于1MB.

If you know your system only has 4MB of usable memory then the 64k page entries can result in more reliable performance. Even with larger memory sizes the interrupt code and data can use 64k entries with TLB lock down ^note to avoid page table walks. This can result in better IRQ latency. The TLB is a limited resource so using 4k entries for the interrupt handler may result in wasting the TLB. Using section entries may waste memory as most interrupt code is <1MB.

即使没有锁定，经常使用的64k条目也很有可能会保留在TLB中.具有每个任务/进程内存的OS可能需要更改MMU表，这可能导致TLB和缓存刷新并失效.为了简化上下文切换，所有内容都可能无效并刷新.因此，通过表进行中断可能比您想像的更普遍.这是使用MMU"PID"功能并且仅刷新/使较小的内存区域无效并使内核代码/数据保留在系统缓存中的一种动机.诸如调度程序之类的其他代码也将受益于64k条目的映射.

Even without lock down, it is more likely that a 64k entry that is frequently used will remain in the TLB. An OS with per task/process memory may need to change the MMU tables which can result in TLB and cache flushing and invalidate. In order to simplify the context switch, everything maybe invalidated and flushed. So a table walk on an interrupt may be more common than you would suspect. This is a motivation to use the MMU 'PID' functionality and to only flush/invalidate smaller regions of memory and allow kernel code/data to remain in system caches. Additional code like the scheduler will also benefit from being mapped by a 64k entry.

注意:ARM720T可能/可能没有锁定，但是某些ARM CPU确实有锁定，并且CPU系列之间的MMU条目相当相似.这个答案适用于许多不同的ARM CPU系列.

Note: The ARM720T may/may not have lock down, but some ARM CPUs do and the MMU entry are fairly similar between CPU families. This answer applies to many different families of ARM CPUs.

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