为什么 ARM 有 64KB 大页面? [英] Why does ARM have 64KB Large Pages?

问题描述

ARM720T 用户手册提到了小页面和大页面.既然 ARM 720T 需要一个 64KB 的页表条目在页表中复制 16 次，为什么不放置 16 个小页 (4KB) 条目来模拟 64KB 的页条目，而不是首先使用大页?

The ARM720T user manual mentions small and large pages. Since the ARM 720T requires a 64KB page table entry to be duplicated 16 times in the page table, why not place 16 small page (4KB) entries to mimic a 64KB page entry instead of using a large page in the first place?

推荐答案

来自 ARM720 TRM，

From the ARM720 TRM,

大页面由 64KB 内存块组成.大页面是支持允许映射大范围的内存中只使用一个条目TLB).扩展了额外的访问控制机制到 16KB 子页面.

Large Pages consist of 64KB blocks of memory. Large Pages are supported to allow mapping of a large region of memory while using only a single entry in the TLB). Additional access control mechanisms are extended to 16KB Sub-Pages.

主要好处是 64k 条目将仅消耗一个 TLB(MMU 页条目缓存).TLB 是 64 个条目，所以 64*4k = 256kB 对比 64*64k = 4MB；显着增加不需要页表查找来寻址的内存量.

The main benefit is a 64k entry will only consume one TLB (MMU page entry cache). The TLB is 64 entries so 64*4k = 256kB versus 64*64k = 4MB; a significant increase in the amount of memory that doesn't require a page table lookup to address.

有很多缺点.例如，便携式操作系统(及其 API)可能需要较小的页面.如果所有条目都是 64k，则可能会产生碎片.部分条目甚至更好，每个条目代表一个 1MB 块，64MB 适合 TLB.通常，该部分更适用于虚拟==物理映射.

There are many down sides. For instance, a portable OS (and it's API) might require the smaller pages. If all entries are 64k fragmentation can result. The section entries are even better with each representing a 1MB chunk with 64MB fitting in the TLB. Generally the section will work better for a virtual==physical mapping.

如果您知道您的系统只有 4MB 的可用内存，那么 64k 页面条目可以带来更可靠的性能.即使具有更大的内存大小，中断代码和数据也可以使用 64k 条目并带有 TLB 锁定 ^note 以避免页表遍历.这会导致更好的 IRQ 延迟.TLB 是一种有限的资源，因此为中断处理程序使用 4k 条目可能会导致浪费 TLB.使用段条目可能会浪费内存，因为大多数中断代码小于 1MB.

If you know your system only has 4MB of usable memory then the 64k page entries can result in more reliable performance. Even with larger memory sizes the interrupt code and data can use 64k entries with TLB lock down ^note to avoid page table walks. This can result in better IRQ latency. The TLB is a limited resource so using 4k entries for the interrupt handler may result in wasting the TLB. Using section entries may waste memory as most interrupt code is <1MB.

即使没有锁定，经常使用的 64k 条目也更有可能保留在 TLB 中.具有每个任务/进程内存的操作系统可能需要更改 MMU 表，这可能导致 TLB 和缓存刷新和无效.为了简化上下文切换，一切都可能失效和刷新.因此，在中断时走桌子可能比您想象的更常见.这是使用 MMU 'PID' 功能并仅刷新/使较小的内存区域无效并允许内核代码/数据保留在系统缓存中的动机.其他代码(如调度程序)也将受益于由 64k 条目映射.

Even without lock down, it is more likely that a 64k entry that is frequently used will remain in the TLB. An OS with per task/process memory may need to change the MMU tables which can result in TLB and cache flushing and invalidate. In order to simplify the context switch, everything maybe invalidated and flushed. So a table walk on an interrupt may be more common than you would suspect. This is a motivation to use the MMU 'PID' functionality and to only flush/invalidate smaller regions of memory and allow kernel code/data to remain in system caches. Additional code like the scheduler will also benefit from being mapped by a 64k entry.

注意: ARM720T 可能/可能没有锁定，但一些 ARM CPU 有锁定，并且 CPU 家族之间的 MMU 条目非常相似.这个答案适用于许多不同的 ARM CPU 系列.

Note: The ARM720T may/may not have lock down, but some ARM CPUs do and the MMU entry are fairly similar between CPU families. This answer applies to many different families of ARM CPUs.

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