如何确定英特尔Sandy Bridge CPU中TLB的大小? [英] How is the size of TLB in Intel's Sandy Bridge CPU determined?

问题描述

Wiki网页( https://en.wikipedia.org/wiki/Sandy_Bridge )提到Data TLB分别具有4KB，2MB和1GB页面的64、32和4个条目.

The wiki webpage(https://en.wikipedia.org/wiki/Sandy_Bridge) mentioned that Data TLB has 64, 32 and 4 entries respectively for 4KB, 2MB and 1GB pages.

我发现这些数字很难理解.桑迪桥(Sandy Bridge)的虚拟地址为48位，这意味着对于4K页，可以有2 ^ 36页，对于2MB和1GB页，应该有2 ^ 27和2 ^ 18页.如果TLB有64个4K页条目，则每个条目的大小应不少于6 + 36 = 42位.为什么2M页上只有32个条目，而不是2 ^ 15(42-27)个条目?

I found these numbers hard to understand. Sandy Bridge has a virtual address of 48 bits, which means for 4K page, there can be 2^36 pages, and for 2MB and 1GB pages, there should be 2^27 and 2^18 pages. If TLB has 64 entries for 4K page, the size of each entry should be no less than 6+36 = 42 bits. Why are there only 32 entries for 2M page, instead of 2^15 (42-27) entries?

我知道在TLB条目中将有其他用于控制目的的位.但是，对于不同的页面大小，该空间不应该保持恒定吗?

I know in TLB entries there will be additional bits for control purpose. But shouldn't that space be constant for different page size?

推荐答案

因为它们是不同 TLB.
在我的Haswell上用 EAX = 2 执行cpuid并对TLB描述符进行解码得到:

Becuase they are different TLBs.
Executing cpuid with EAX=2 on my Haswell and decoding the TLB descriptors gets:

说明TLB :
              2M/4M页，完全关联，有8个条目
             4KB的页面，8路，64个条目

Instruction TLB:
              2M/4M pages, fully associative, 8 entries
              4KByte pages, 8-way, 64 entries

数据TLB :
             2M/4M页，4向，32个条目和单独的数组 1 GB 页，四向，四项，
              4 KB页面，4路，共64个条目

Data TLB:
              2M/4M pages, 4-way, 32 entries and a separate array with 1 GByte pages, 4-way, 4 entries
              4 KByte pages, 4-way, 64 entries

共享的二级TLB :
             4 K/2M页，8路，1024个条目

Shared 2nd-Level TLB:
              4 K/2M pages, 8-way, 1024 entries

TLB缓存是高度专业化的 CAM ，固定布局，它不是具有通用布局的暂存器.

A TLB cache is a highly specialized CAM with a fixed layout, it is not a scratch memory with a general purpose layout.

某些TLB可以处理一个以上的页面大小，但是如果要以一种通用格式缓存信息，则这是一个折衷.
使用不同的TLB处理不同的页面大小可以提高缓存命中率，就像使用DTLB和ITLB一样.

Some TLB can handle more that one page size but those are trade-offs were the information is cached in a common format.
Having different TLBs handling different page sizes improves cache hits, just like having a DTLB and an ITLB.

数据缓存的工作方式有所不同，因为它们不缓存信息，它们缓存的数据没有布局，这就是为什么在其中以KiB的大小为其指定大小，但不适用于处理结构化信息的缓存.

Data caches works differently since they don't cache information, they cache data with no layout and that's why it makes sense to give the size in KiB for them but it doesn't for caches that deal with structured information.

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