和VHDL中n位数组的所有元素 [英] AND all elements of an n-bit array in VHDL

问题描述

让我说我有一个n位数组.我想和数组中的所有元素.类似于将每个元素连接到n位AND门.

lets say I have an n-bit array. I want to AND all elements in the array. Similar to wiring each element to an n-bit AND gate.

如何在VHDL中实现这一目标?

How do I achieve this in VHDL?

注意:我正在尝试使用可重复使用的VHDL代码，所以我想避免对类似的代码进行硬编码

Note: I am trying to use re-usable VHDL code so I want to avoid hard coding something like

    result <= array(0) and array(1) and array(2)....and array(n); 

谢谢 奥斯拉

推荐答案

解决方案1:使用一元运算符

VHDL-2008定义一元运算符，如下所示:

VHDL-2008 defines unary operators, like these:

outp <= and "11011";
outp <= xor "11011";
outp <= and inp; --this would be your case

但是，您的编译器可能尚不支持它们.

However, they might not be supported yet by your compiler.

解决方案2:使用纯组合(和传统)代码

由于在并发代码中不能多次为一个信号分配一个值，因此可以创建一个尺寸为额外"的温度信号.在您的情况下，输出为一位，因此温度信号应为一维数组，如下所示.

Because in concurrent code you cannot assign a value to a signal more than once, your can create a temp signal with an "extra" dimension. In your case, the output is one-bit, so the temp signal should be a 1D array, as shown below.

-------------------------------------------
entity unary_AND IS
    generic (N: positive := 8); --array size
    port (
        inp: in bit_vector(N-1 downto 0);
        outp: out bit);
end entity;
-------------------------------------------
architecture unary_AND of unary_AND is
    signal temp: bit_vector(N-1 downto 0);
begin
    temp(0) <= inp(0);
    gen: for i in 1 to N-1 generate
        temp(i) <= temp(i-1) and inp(i);
    end generate; 
    outp <= temp(N-1); 
end architecture;
-------------------------------------------

推断的电路如下图所示.

The inferred circuit is shown in the figure below.

解决方案3:使用顺序代码

这比解决方案2更简单，尽管您现在使用顺序代码来解决纯粹的组合问题(但是硬件是相同的).您可以编写与解决方案2类似的代码，但使用 process 和 loop (后者代替 generate )或使用功能.因为在顺序代码中，您可以多次给一个信号分配一个值，所以这里不需要解决方案2的温度信号.

This is simpler than solution 2, though you are now using sequential code to solve a purely combinational problem (but the hardware will be the same). You can either write a code similar to that in solution 2, but with a process and loop (the latter, in place of generate) or using a function. Because in sequential code you are allowed to assign a value to a signal more than once, the temp signal of solution 2 is not needed here.

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