VHDL代码上的TimeQuest中的“无报告路径" [英] 'No paths to report' in TimeQuest on VHDL code

问题描述

我正在Altera Quartus 13.1中编写一些代码，但无法在TimeQuest中检查我的实体的Fmax.我得到没有报告途径".代码如下:

I'm writting some code in Altera Quartus 13.1 and I can't check my Fmax for my entity in TimeQuest. I get 'No paths to report'. The code is given below:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

library NTRU;
use NTRU.NTRU.all;

entity ModuloAdder is
    port(
        FirstHalf   : in Int32 := 0;
        SecondHalf  : in Int32 := 0;    
        Start           : in std_logic := '0';
        clk             : in std_logic;
        Result      : out Int32 := 0;
        ReadyOut        : out std_logic
        );
end ModuloAdder;

architecture a1 of ModuloAdder is
begin
process(clk, Start, FirstHalf, SecondHalf)
variable sum: integer range 63 downto -63:=0;
begin
    if clk'event and clk ='1' then
        if Start = '1' then 
            sum := (FirstHalf + SecondHalf) mod 32;
            if sum > 32 then
                Result <= sum mod 32;
            elsif sum < -3 then
                Result <= sum+32;
            else 
                Result <= sum;
            end if;
            ReadyOut <= '1';
        else 
            ReadyOut <= '0';
            Result <= 0;
        end if;
    end if;
end process;
end a1;

我的问题是为什么会出现此问题.当我将变量和更改为信号时，一切正常，但我希望在一个时钟周期内完成.该代码在ModelSim中可以正常工作，并且可以提供良好的结果.

My question is why this problem occur. When I change variable sum to signal, there is everything ok, but I want this in one clock cycle. This code works fine in ModelSim and is giving fine results.

推荐答案

在您的设计中似乎没有寄存器来注册路径，因此TimeQuest无法报告Fmax.要报告Fmax，您必须告诉它I/O信号和clk之间的关系(使用set_input_delay和set_output_delay).或者，如果您首先注册输入(例如，通过添加 FirstHalfReg< = FirstHalf )，则应该看到注册要注册的路径，并且应该获得这些内部路径的Fmax.

It looks like there are no register to register paths in your design, so TimeQuest can't report an Fmax. To report an Fmax, you'd have to tell it the relationship between the I/O signals and the clk (using set_input_delay and set_output_delay). Or, if you first register your inputs (e.g. by adding FirstHalfReg <= FirstHalf), you should see register to register, paths, and should get an Fmax for those internal paths.

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